Output SYNC can be used to phase-align two or more output clocks with a common rising edge by allowing the output dividers to exit reset on the same PLL output clock cycle. Any output dividers selecting the same PLL output can be synchronized together as a SYNC group by triggering a SYNC event through the hardware pin or software bit.

The following requirements must be met to establish a SYNC group for two or more output channels:

• Output dividers have their respective SYNC enable bit set (CHx_SYNC_EN = 1).
• Output dividers have their output mux selecting the same PLL output.
• The PLL (post-divider) output has its SYNC enable bit set (for example, PLL1_P1_SYNC_EN = 1).

A SYNC event can be asserted by the hardware GPIO0/SYNCN pin (active low) or the SYNC_SW register bit (active high). When SYNC is asserted, the SYNC-enabled dividers held are reset and clock outputs are muted. When SYNC is deasserted, the outputs will start with their initial clock phases synchronized or aligned. SYNC can also be used to mute any SYNC-enabled outputs to prevent output clocks from being distributed to downstream devices until they are configured and ready to accept the incoming clock.

Output channels with their SYNC disabled (CHx_SYNC_EN bit = 0) will not be affected by a SYNC event and will continue normal output operation as configured. Also, VCO and PLL post-divider clocks do not stop running during the SYNC so they can continue to source output channels that do not require synchronization. Output dividers with divide-by-1 (divider bypass mode) are not gated during the SYNC event.