ZHCSN15B June 2020 – June 2021 LMK05318B
PRODUCTION DATA
For the DPLL block, the reference input mux selection can be done automatically using an internal state machine with a configurable input priority scheme, or manually through software register control or hardware pin control. The input mux can select from PRIREF or SECREF. The priority for all inputs can be assigned through registers. The priority ranges from 0 to 2, where 0 = ignore (never select), 1 = first priority, and 2 = second priority. When both inputs are configured with the same priority setting, PRIREF will be given first priority. The selected input can be monitored through the status pins or register.