米6体育平台手机版

ZHCSN15B June 2020 – June 2021 LMK05318B

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

RGZ|48
- MPQF123F

散热焊盘机械数据 (封装 | 引脚)

RGZ|48
- QFND031W

订购信息

7.6 Electrical Characteristics

Over Recommended Operating Conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLY CHARACTERISTICS
IDD_DIG	Core Current Consumption (VDD_DIG)			21		mA
IDD_IN	Core Current Consumption (VDD_IN)			43		mA
IDD_PLL1	Core Current Consumption (VDD_PLL1)	DPLL and APLL1 enabled		110		mA
IDD_XO	Core Current Consumption (VDD_XO)			20		mA
IDD_PLL2	Core Current Consumption (VDD_PLL2)	APLL2 disabled		20		mA
IDD_PLL2	Core Current Consumption (VDD_PLL2)	APLL2 enabled		120		mA
IDDO_x	Output Current Consumption, per channel⁽³⁾ (VDDO_x)	Output mux and divider enabled, excludes driver(s) Divider value = 2 to 6		65		mA
		Output mux and divider enabled, excludes driver(s) Divider value > 6		70		mA
		AC-LVDS		11		mA
		AC-CML		16		mA
		AC-LVPECL		18		mA
		HCSL, 50-Ω load to GND		25		mA
		1.8-V LVCMOS (x2), 100 MHz		6		mA
IDD_PDN	Total Current Consumption (all VDD and VDDO pins, 3.3 V)	Device powered-down (PDN pin held low)		56		mA
XO INPUT CHARACTERISTICS (XO)
f_IN	Input frequency range		10		100	MHz
V_IN-SE	Single-ended input voltage swing	LVCMOS input, DC-coupled to XO_P	1		2.6	Vpp
V_IN-DIFF	Differential input voltage swing⁽¹¹⁾	Differential input	0.4		2	Vpp
V_ID	Differential input voltage swing⁽¹¹⁾	Differential input	0.2		1	\|V\|
dV/dt	Input slew rate⁽¹³⁾		0.2	0.5		V/ns
IDC	Input duty cycle		40		60	%
I_IN	Input leakage	50-Ω and 100-Ω internal terminations disabled	–350		350	µA
REFERENCE INPUT CHARACTERISTICS (PRIREF, SECREF)
f_IN	Input frequency range	Differential input⁽⁴⁾	5		800	MHz
f_IN	Input frequency range	LVCMOS input	1E–6		250	MHz
V_IH	Input high voltage	LVCMOS input, DC-coupled to REF_P. Internally DC-coupled	1.8			V
V_IL	Input low voltage	LVCMOS input, DC-coupled to REF_P. Internally DC-coupled			0.6	V
V_IN-SE	Single-ended input voltage swing	LVCMOS input, DC-coupled to REF_P. Internally AC-coupled	1		2.6	Vpp
V_IN-DIFF	Differential input voltage swing⁽¹¹⁾	Differential input, , V_HYST = 50 mV	0.4		2	Vpp
V_IN-DIFF	Differential input voltage swing⁽¹¹⁾	Differential input, , V_HYST = 200 mV	0.7		2	Vpp
V_ID	Differential input voltage swing⁽¹¹⁾	Differential input, V_HYST = 50 mV	0.2		1	V
V_ID	Differential input voltage swing⁽¹¹⁾	Differential input, V_HYST = 200 mV	0.35		1	V
dV/dt	Input slew rate⁽¹³⁾		0.2	0.5		V/ns
I_IN	Input leakage	50-Ω and 100-Ω internal terminations disabled	–350		350	µA
VCO CHARACTERISTICS
f_VCO1	VCO1 Frequency Range		2499.750	2500	2500.250	MHz
f_VCO2	VCO2 Frequency Range		5500		6250	MHz
APLL CHARACTERISTICS
f_PD1	APLL1 Phase Detector Frequency		1		80	MHz
f_PD2	APLL2 Phase Detector Frequency		10		150	MHz
AC-LVDS OUTPUT CHARACTERISTICS (OUTx)
f_OUT	Output frequency⁽⁵⁾				1250	MHz
V_OD	Output voltage swing (V_OH - V_OL)	25 MHz ≤ f_OUT ≤ 800 MHz; TYP at 156.25 MHz	250	390	450	mV
		f_OUT = 50 MHz	285	400	450
		100 MHz ≤ f_OUT ≤ 200 MHz	275	390	450
		f_OUT = 312.5	270	385	450
		f_OUT = 1250 MHz		280
V_OUT-DIFF	Differential output voltage swing, peak-to-peak			2×V_OD		Vpp
V_OS	Output common mode		100		430	mV
t_SK	Output-to-output skew	Same post divider, output divide values, and output type			100	ps
t_R/t_F	Output rise/fall time⁽¹²⁾	20% to 80%, < 300 MHz		225	350	ps
t_R/t_F	Output rise/fall time⁽¹²⁾	± 100 mV around center point, 300 MHz ≤ f_OUT ≤ 800 MHz		85	250	ps
PN_FLOOR	Output phase noise floor	f_OUT = 156.25 MHz; f_OFFSET > 10 MHz		-160		dBc/Hz
ODC	Output duty cycle⁽⁹⁾		45		55	%
AC-CML OUTPUT CHARACTERISTICS (OUTx)
f_OUT	Output frequency⁽⁵⁾				1250	MHz
V_OD	Output voltage swing (V_OH - V_OL)	25 MHz ≤ f_OUT ≤ 800 MHz; TYP at f_OUT = 156.25 MHz	400	600	800	mV
		f_OUT = 50 MHz	500	620	700
		100 MHz ≤ f_OUT ≤ 200 MHz	490	600	690
		f_OUT = 312.5	480	580	680
		f_OUT = 1250 MHz		400
V_OUT-DIFF	Differential output voltage swing, peak-to-peak			2×V_OD		Vpp
V_OS	Output common mode		150		550	mV
t_SK	Output-to-output skew	Same post divider, output divide values, and output type			100	ps
t_R/t_F	Output rise/fall time⁽¹²⁾	20% to 80%, < 300 MHz		225	300	ps
t_R/t_F	Output rise/fall time⁽¹²⁾	± 100 mV around center point, 300 MHz ≤ f_OUT ≤ 800 MHz		50	150	ps
PN_FLOOR	Output phase noise floor	f_OUT = 156.25 MHz; f_OFFSET > 10 MHz		-160		dBc/Hz
ODC	Output duty cycle⁽⁹⁾		45		55	%
AC-LVPECL OUTPUT CHARACTERISTICS (OUTx)
f_OUT	Output frequency⁽⁵⁾				1250	MHz
V_OD	Output voltage swing (V_OH - V_OL)	25 MHz ≤ f_OUT ≤ 800 MHz; TYP at f_OUT = 156.25 MHz	500	780	1000	mV
		f_OUT = 50 MHz	660	810	920
		100 MHz ≤ f_OUT ≤ 200 MHz	640	780	900
		f_OUT = 312.5 MHz	620	740	880
		f_OUT = 1250 MHz		510
V_OUT-DIFF	Differential output voltage swing, peak-to-peak			2×V_OD		Vpp
V_OS	Output common mode		300		700	mV
t_SK	Output-to-output skew	Same post divider, output divide values, and output type			100	ps
t_R/t_F	Output rise/fall time⁽¹²⁾	20% to 80%, < 300 MHz		200	300	ps
t_R/t_F	Output rise/fall time⁽¹²⁾	± 100 mV around center point, 300 MHz ≤ f_OUT ≤ 800 MHz		35	100	ps
PN_FLOOR	Output phase noise floor	f_OUT = 156.25 MHz; f_OFFSET > 10 MHz		–162		dBc/Hz
ODC	Output duty cycle⁽⁹⁾		45		55	%
HCSL OUTPUT CHARACTERISTICS (OUTx)
f_OUT	Output frequency⁽⁵⁾				400	MHz
V_OH	Output high voltage		600		880	mV
V_OL	Output low voltage		–150		150	mV
t_SK	Output-to-output skew	Same post divider, output divide values, and output type			100	ps
dV/dt	Output slew rate⁽¹²⁾	± 150 mV around center point	1.6		4	V/ns
PN_FLOOR	Output phase noise floor (f_OFFSET > 10 MHz)	100 MHz		–160		dBc/Hz
ODC	Output duty cycle⁽⁹⁾		45		55	%
1.8-V LVCMOS OUTPUT CHARACTERISTICS (OUT[4:7])
f_OUT	Output frequency		1E–6		200	MHz
V_OH	Output high voltage	I_OH = 1 mA	1.2			V
V_OL	Output low voltage	I_OL = 1 mA			0.4	V
I_OH	Output high current			–23		mA
I_OL	Output low current			20		mA
t_R/t_F	Output rise/fall time	20% to 80%		250		ps
t_SK	Output-to-output skew	Same post divider, output divide values, and output type			100	ps
t_SK	Output-to-output skew	Same post divider, output divide values, LVCMOS-to-DIFF			1.5	ns
PN_FLOOR	Output phase noise floor	f_OUT = 66.66 MHz; f_OFFSET > 10 MHz		-160		dBc/Hz
ODC	Output duty cycle⁽⁹⁾		45		55	%
R_OUT	Output impedance			50		Ω
3-LEVEL LOGIC INPUT CHARACTERISTICS (HW_SW_CTRL, GPIO1, REFSEL, STATUS[1:0])
V_IH	Input high voltage		1.4			V
V_IM	Input mid voltage	Input floating with internal bias and PDN pulled low	0.7		0.9	V
V_IL	Input low voltage				0.4	V
I_IH	Input high current	V_IH = VDD	–40		40	µA
I_IL	Input low current	V_IL = GND	–40		40	µA
2-LEVEL LOGIC INPUT CHARACTERISTICS (PDN, GPIO[2:0], SDI, SCK, SCS)
V_IH	Input high voltage		1.2			V
V_IL	Input low voltage				0.6	V
I_IH	Input high current	V_IH = VDD	-40		40	µA
I_IL	Input low current	V_IL = GND	-40		40	µA
LOGIC OUTPUT CHARACTERISTICS (STATUS[1:0], SDO)
V_OH	Output high voltage	I_OH = 1 mA	1.2			V
V_OL	Output low voltage	I_OL = 1 mA			0.6	V
t_R/t_F	Output rise/fall time	20% to 80%, LVCMOS mode, 1 kΩ to GND		500		ps
SPI TIMING REQUIREMENTS (SDI, SCK, SCS, SDO)
f_SCK	SPI clock rate				20	MHz
f_SCK	SPI clock rate; NVM write				5	MHz
t₁	SCS to SCK setup time		10			ns
t₂	SDI to SCK setup time		10			ns
t₃	SDI to SCK hold time		10			ns
t₄	SCK high time		25			ns
t₅	SCK low time		25			ns
t₆	SCK to SDO valid read-back data				20	ns
t₇	SCS pulse width		20			ns
t₈	SDI to SCK hold time		10			ns
I²C-COMPATIBLE INTERFACE CHARACTERISTICS (SDA, SCL)
V_IH	Input high voltage		1.2			V
V_IL	Input low voltage				0.6	V
I_IH	Input leakage		–15		15	µA
V_OL	Output low voltage	I_OL = 3 mA			0.3	V
f_SCL	I²C clock rate	Standard			100	kHz
f_SCL	I²C clock rate	Fast mode			400	kHz
t_SU(START)	START condition setup time	SCL high before SDA low	0.6			µs
t_H(START)	START condition hold time	SCL low after SDA low	0.6			µs
t_W(SCLH)	SCL pulse width high		0.6			µs
t_W(SCLL)	SCL pulse width low		1.3			µs
t_SU(SDA)	SDA setup time		100			ns
t_H(SDA)	SDA hold time	SDA valid after SCL low	0		0.9	µs
t_R(IN)	SDA/SCL input rise time				300	ns
t_F(IN)	SDA/SCL input fall time				300	ns
t_F(OUT)	SDA output fall time	C_BUS ≤ 400 pF			300	ns
t_SU(STOP)	STOP condition setup time		0.6			µs
t_BUS	Bus free time between STOP and START		1.3			µs
POWER SUPPLY NOISE REJECTION (PSNR) / CROSSTALK SPURS
PSNR_50mV	Spur induced by power supply noise (V_N = 50 mVpp) ⁽⁶⁾ ⁽⁷⁾	V_DD = 3.3 V, V_{DDO_x} = 3.3 V, 156.25 MHz, AC-DIFF output		–83		dBc
PSNR_50mV	Spur induced by power supply noise (V_N = 50 mVpp) ⁽⁶⁾ ⁽⁷⁾	V_DD = 3.3 V, V_{DDO_x} = 3.3 V, 156.25 MHz, HCSL output		–78		dBc
PSNR_25mV	Spur induced by power supply noise (V_N = 25 mVpp)⁽⁶⁾ ⁽⁷⁾	V_DD = 3.3 V, V_{DDO_x} = 1.8 V, 156.25 MHz, AC-DIFF output		–63		dBc
		V_DD = 3.3 V, V_{DDO_x} = 1.8 V, 156.25 MHz, HCSL output		–58		dBc
		V_DD = 3.3 V, V_{DDO_x} = 1.8 V, 156.25 MHz, LVCMOS output		–45		dBc
SPUR_XTALK	Spur level due to output-to-output crosstalk (adjacent channels)⁽⁷⁾	f_OUTx = 156.25 MHz, f_OUTy = 155.52 MHz, AC-LVPECL		–75		dBc
SPUR	Highest spur level within 12 kHz to 40 MHz band (excludes output crosstalk and integer-boundary spurs)⁽⁷⁾	f_VCO1 = 2500 MHz, f_VCO2 = 6065.28 MHz, f_OUTx = 156.25 MHz, f_OUTy = 155.52 MHz, AC-LVPECL		–80		dBc
PLL CLOCK OUTPUT PERFORMANCE CHARACTERISTICS
RJ	RMS Phase Jitter (12 kHz to 20 MHz)⁽¹⁴⁾	312.5 MHz AC-LVPECL output from APLL1, f_XO = 48.0048 MHz, f_PD1 = f_XO/2, f_VCO1 = 2.5 GHz		50	80	fs RMS
	RMS Phase Jitter (12 kHz to 20 MHz)⁽¹⁴⁾	156.25 MHz AC-LVPECL output from APLL1, f_XO = 48.0048 MHz, f_PD1 = f_XO/2, f_VCO1 = 2.5 GHz		60	90	fs RMS
	RMS Phase Jitter (12 kHz to 20 MHz)⁽¹⁴⁾	153.6 MHz AC-LVPECL output from APLL2, f_XO = 48.0048 MHz, f_PD1 = f_XO/2, f_VCO1 = 2.5 GHz, f_PD2 = f_VCO1/18, f_VCO2 = 5.5296 GHz		125	200	fs RMS
	RMS Phase Jitter (12 kHz to 20 MHz)⁽¹⁴⁾	155.52 MHz AC-LVPECL output from APLL2, f_XO = 48.0048 MHz, f_PD1 = f_XO/2, f_VCO1 = 2.5 GHz, f_PD2 = f_VCO1/18, f_VCO2 = 5.59872 GHz		125	200	fs RMS
BW	DPLL bandwidth range⁽⁸⁾	Programmed bandwidth setting	0.01		4000	Hz
J_PK	DPLL closed-loop jitter peaking⁽¹⁰⁾	f_REF = 25 MHz, f_OUT = 10 MHz, DPLL BW = 0.1 Hz or 10 Hz		0.1		dB
J_TOL	Jitter tolerance	Jitter modulation = 10 Hz, 25.78125 Gbps		6455		UI p-p
t_HITLESS	Phase hit between two reference inputs with 0 ppm error	Valid for a single switchover event between two clock inputs at the same frequency		± 50		ps
f_HITLESS	Frequency transient during hitless switch	Valid for a single switchover event between two clock inputs at the same frequency		± 10		ppb

(1) Total device current can be estimated by summing the individual IDD_x and IDDO_x per pin for all blocks enabled in a given configuration.

(5) Configuration A (All PLL blocks on except APLL2 is disabled): f_REF = 25 MHz, f_XO = 48.0048 MHz, f_VCO1 = 2.5 GHz.

(5) Configuration B (All PLL blocks on): f_REF = 25 MHz, f_XO = 48.0048 MHz, f_VCO1 = 2.5 GHz, f_VCO2 = 5598.72 GHz, PLL2_P1 = 3.

(6) IDDO_x current for an operating output is the sum of mux, divider, and an output format.

(8) For a differential input clock below 5 MHz, TI recommends to disable the differential input amplitude monitor and enable at least one other monitor (frequency, window detectors) to validate the input clock. Otherwise, consider using an LVCMOS clock for an input below 5 MHz.

(5) An output frequency over f_OUT max spec is possible, but output swing may be less than V_OD min specification.

(6) PSNR is the single-sideband spur level (in dBc) measured when sinusoidal noise with ampitude V_N and frequency f_N (between 100 kHz and 1 MHz) is injected onto VDD and VDDO_x pins.

(7) DJ_SPUR (ps pk-pk) = [2 × 10^(dBc/20) / (π × f_OUT) × 1E6], where dBc is the PSNR or SPUR level (in dBc) and f_OUT is the output frequency (in MHz).

(8) Actual loop bandwidth may be lower. The valid loop bandwidth range may be constrained by the DPLL TDC frequency used in a given configuration.

(9) Parameter is specified for PLL outputs divided from either VCO domain.

(10) DPLL closed-loop jitter peaking of 0.1 dB or less is based on the DPLL bandwidth setting configured by the TICS Pro software tool.

(11) Minimum limit applies for the minimum setting of the differential input amplitude monitor (xREF_LVL_SEL = 0).

(12) Measured on the differential output waveform (OUTx_P - OUTx_N). Output with 2-pF load.

(13) To meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. TI also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs.

(14) Excluding output coupling spurs