The LMK1D1204P shown in Figure 10-1 is configured to select two inputs: a 156.25-MHz LVDS clock from the backplane, or a secondary 156.25-MHz, LVCMOS, 2.5-V oscillator. The LVDS clock is AC-coupled and biased using the integrated reference voltage generator. A resistor divider is used to set the threshold voltage correctly for the LVCMOS clock. 0.1-µF capacitors are used to reduce noise on both V_{AC_REF} and SECREF_N. Either input signal can be then fanned out to desired devices, as shown. The configuration example is driving 4 LVDS receivers in a line card application with the following properties:

• The PHY device is capable of DC coupling with an LVDS driver such as the LMK1D1204P. This PHY device features internal termination so no additional components are required for proper operation.
• The ASIC LVDS receiver features internal termination and operates at the same common-mode voltage as the LMK1D1204P. Again, no additional components are required.
• The FPGA requires external AC coupling, but has internal termination. 0.1-µF capacitors are placed to provide AC coupling. Similarly, the CPU is internally terminated, and requires only external AC-coupling capacitors.
• The unused outputs of the LMK1D1204P can be disabled using the corresponding OEx pin. This results in a lower power consumption.