ZHCSP66A october 2021 – april 2023 LMK1D1212 , LMK1D1216
PRODUCTION DATA
The LMK1D121x is a low additive jitter LVDS fan-out buffer that can generate up to 12 (LMK1D1212) or 16 (LMK1D1216) copies of two selectable LVPECL, LVDS, LP-HCSL, HCSL, or LVCMOS inputs. The LMK1D121x can accept reference clock frequencies up to 2 GHz while providing low output skew.
Table 9-2 lists the LMK1D1212 and LMK1D1216outputs divided into two banks.
| Bank | LMK1D1212 | LMK1D1216 |
|---|---|---|
| 0 | OUT0 to OUT5 | OUT0 to OUT7 |
| 1 | OUT6 to OUT11 | OUT8 to OUT15 |
Apart from providing a very low additive jitter and low output skew, the LMK1D121x has an input select pin (IN_SEL) and an output amplitude control pin (AMP_SEL).