ZHCSP66A october   2021  – april 2023 LMK1D1212 , LMK1D1216

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fail-Safe Input and Hysteresis
      2. 9.3.2 Input Mux
    4. 9.4 Device Functional Modes
      1. 9.4.1 LVDS Output Termination
      2. 9.4.2 Input Termination
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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7.5 Electrical Characteristics

VDD = 1.8 V ± 5 %, –40°C ≤T_A ≤ 105°C. Typical values are at VDD = 1.8 V, 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY CHARACTERISTICS
IDDSTAT Core supply current, static (LMK1D1212) All outputs enabled and unterminated, f = 0 Hz  65 mA
IDDSTAT Core supply current, static (LMK1D1216) All outputs enabled and unterminated, f = 0 Hz 70 mA
IDD100M Core supply current (LMK1D1212) All outputs enabled, RL = 100 Ω, f =100 MHz 105 130 mA
IDD100M Core supply current (LMK1D1216) All outputs enabled, RL = 100 Ω, f =100 MHz 120 150 mA
IN_SEL/AMP_SEL CONTROL INPUT CHARACTERISTICS (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
VdI3 Tri-state input Open 0.4 × VCC V
VIH Input high voltage Minimum input voltage for a logical "1" state in table 1 0.7 × VCC VCC + 0.3 V
VIL Input low voltage Maximum input voltage for a logical "0" state in table 1 –0.3 0.3 × VCC V
IIH Input high current VDD can be 1.8V, 2.5V, or 3.3V with VIH = VDD 30 µA
IIL Input low current VDD can be 1.8V, 2.5V, or 3.3V with VIH = VDD –30 µA
Rpull-up Input pullup resistor 500 kΩ
Rpull-down Input pulldown resistor 320 kΩ
SINGLE-ENDED LVCMOS/LVTTL CLOCK INPUT (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
fIN Input frequency Clock input DC 250 MHz
VIN_S-E Single-ended Input Voltage Swing Assumes a square wave input with two levels 0.4 3.465 V
dVIN/dt Input Slew Rate (20% to 80% of the amplitude) 0.05 V/ns
IIH Input high current VDD = 3.465 V, VIH = 3.465 V 60 µA
IIL Input low current VDD = 3.465 V, VIL = 0 V –30 µA
CIN_SE Input capacitance at 25°C 3.5 pF
DIFFERENTIAL CLOCK INPUT (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
fIN Input frequency Clock input 2 GHz
VIN,DIFF(p-p) Differential input voltage peak-to-peak {2 × (VINP – VINN)} VICM = 1 V (VDD = 1.8 V) 0.3 2.4 VPP
VICM = 1.25 V (VDD = 2.5 V/3.3 V) 0.3 2.4
VICM Input common-mode voltage VIN,DIFF(P-P) > 0.4 V (VDD = 1.8 V/2.5 V/3.3 V) 0.25 2.3 V
IIH Input high current VDD = 3.465 V, VINP = 2.4 V, VINN = 1.2 V 30 µA
IIL Input low current VDD = 3.465 V, VINP = 0 V, VINN = 1.2 V –30 µA
CIN_SE Input capacitance (Single-ended) at 25°C 3.5 pF
LVDS DC OUTPUT CHARACTERISTICS
|VOD| Differential output voltage magnitude |VOUTP - VOUTN| VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω 250 350 450 mV
|VOD| Differential output voltage magnitude |VOUTP - VOUTN| VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω, AMP_SEL = 1 400 500 650 mV
ΔVOD Change in differential output voltage magnitude VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω –15 15 mV
ΔVOD Change in differential output voltage magnitude VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω, AMP_SEL = 1 –20 20 mV
VOC(SS) Steady-state, common-mode output voltage VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω (VDD = 1.8 V) 1 1.2 V
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω (VDD = 2.5 V/3.3 V) 1.1 1.375
VOC(SS) Steady-state, common-mode output voltage VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω (VDD = 1.8 V), AMP_SEL = 1 0.8 1.05 V
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω (VDD = 2.5 V/3.3 V), AMP_SEL = 1 0.9 1.15
ΔVOC(SS) Change in steady-state, common-mode output voltage VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω –15 15 mV
ΔVOC(SS) Change in steady-state, common-mode output voltage VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω, AMP_SEL = 1 –20 20 mV
LVDS AC OUTPUT CHARACTERISTICS
Vring Output overshoot and undershoot VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω, fOUT = 491.52 MHz –0.1 0.1 VOD
VOS Output AC common-mode voltage VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω 50 100 mVpp
VOS Output AC common-mode voltage VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω, AMP_SEL = 1 75 150 mVpp
IOS Short-circuit output current (differential) VOUTP = VOUTN –12 12 mA
IOS(cm) Short-circuit output current (common-mode) VOUTP = VOUTN = 0 –24 24 mA
tPD Propagation delay VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω (1) 0.3 0.575 ns
tSK, O Output skew Skew between outputs with the same load conditions (12 and 16 channels) (2) 20 ps
tSK, PP Part-to-part skew Skew between outputs on different parts subjected to the same operating conditions with the same input and output loading. 200 ps
tSK, P Pulse skew 50% duty cycle input, crossing point-to-crossing-point distortion (3) –20 20 ps
tRJIT(ADD) Random additive Jitter (rms) fIN = 156.25 MHz with 50% duty-cycle, Input slew rate = 1.5V/ns, Integration range = 12 kHz to 20 MHz, with output load RLOAD = 100 Ω 45 60 fs, RMS
Phase noise Phase Noise for a carrier frequency of 156.25 MHz with 50% duty-cycle, Input slew rate = 1.5V/ns with output load RLOAD = 100 Ω  PN1kHz  –143 dBc/Hz
PN10kHz  –150
PN100kHz –157
PN1MHz  –160
PNfloor  –164
MUXISO Mux Isolation fIN = 156.25 MHz. The difference in power level at fIN when the selected clock is active and the unselected clock is static versus when the selected clock is inactive and the unselected clock is active. 80 dB
ODC Output duty cycle With 50% duty cycle input 45 55 %
tR/tF Output rise and fall time 20% to 80% with RLOAD = 100 Ω 300 ps
tR/tF Output rise and fall time 20% to 80% with RLOAD = 100 Ω (AMP_SEL= 1) 300 ps
VAC_REF Reference output voltage VDD = 2.5 V, ILOAD = 100 μA 0.9 1.25 1.375 V
POWER SUPPLY NOISE REJECTION (PSNR) VDD = 2.5 V/ 3.3 V
PSNR Power Supply Noise Rejection (fcarrier = 156.25 MHz) 10 kHz, 100 mVpp ripple injected on VDD –70 dBc
1 MHz, 100 mVpp ripple injected on VDD –50
(1) Measured between single-ended/differential input crossing point to the differential output crossing point.
(2) For the dual bank devices, the inputs are phase aligned and have 50% duty cycle.
(3) Defined as the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
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