ZHCSOY4B september 2021 – june 2023 LMK1D2102 , LMK1D2104
PRODUCTION DATA
6 Pin Configuration and Functions
Figure 6-1 LMK1D2102: RGT Package 16-Pin VQFN Top View
Figure 6-2 LMK1D2104: RHD Package 28-Pin VQFN Top ViewTable 6-1 Pin Functions
| PIN | TYPE(1) | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | LMK1D2102 | LMK1D2104 | ||
| DIFFERENTIAL/SINGLE-ENDED CLOCK INPUT | ||||
| IN0_P, IN0_N | 6, 7 | 9, 10 | I | Primary: Differential input pair or single-ended input |
| IN1_P, IN1_N | 3, 4 | 5, 6 | I | Secondary: Differential input pair or single-ended input. |
| Note that INP0, INN0 are used indistinguishably with IN0_P, IN0_N. | ||||
| OUTPUT BANK CONTROL | ||||
| EN | 2 | 4 | I | Output bank enable/disable with an internal 500-kΩ pullup and 320-kΩ pulldown, selects input port; (See Table 9-1) |
| BIAS VOLTAGE OUTPUT | ||||
| VAC_REF0,VAC_REF1 | 8 | 11, 7 | O | Bias voltage output for capacitive coupled inputs. If used, TI recommends using a 0.1-µF capacitor to GND on this pin. |
| DIFFERENTIAL CLOCK OUTPUT | ||||
| OUT0_P, OUT0_N | 9, 10 | 12, 13 | O | Differential LVDS output pair number 0 |
| OUT1_P, OUT1_N | 11, 12 | 16, 17 | O | Differential LVDS output pair number 1 |
| OUT2_P, OUT2_N | 13, 14 | 18, 19 | O | Differential LVDS output pair number 2 |
| OUT3_P, OUT3_N | 15, 16 | 20, 21 | O | Differential LVDS output pair number 3 |
| OUT4_P, OUT4_N | 22, 23 | O | Differential LVDS output pair number 4 | |
| OUT5_P, OUT5_N | 24, 25 | O | Differential LVDS output pair number 5 | |
| OUT6_P, OUT6_N | 26, 27 | O | Differential LVDS output pair number 6 | |
| OUT7_P, OUT7_N | 2, 3 | O | Differential LVDS output pair number 7 | |
| SUPPLY VOLTAGE | ||||
| VDD | 5 | 8, 15, 28 | P | Device Power Supply (1.8V or 2.5V or 3.3V) |
| GROUND | ||||
| GND | 1 | 1, 14 | G | Ground |
| DAP | DAP | DAP |
G |
Die Attach Pad. Connect to the PCB ground plane for heat dissipation. |
(1) G = Ground, I = Input, O = Output, P = Power