5 Pin Configuration and Functions

Figure 5-1 LMK1D2106: RHA Package 40-Pin VQFN Top View

Figure 5-2 LMK1D2108: RGZ Package 48-Pin VQFN Top View

Table 5-1 Pin Functions

PIN			TYPE⁽¹⁾	DESCRIPTION
NAME	LMK1D2106	LMK1D2108	TYPE⁽¹⁾	DESCRIPTION
DIFFERENTIAL/SINGLE-ENDED CLOCK INPUT
IN0_P, IN0_N	8, 9	9, 10	I	Primary: Differential input pair or single-ended input
IN1_P, IN1_N	2, 3	3, 4	I	Secondary: Differential input pair or single-ended input
IN1_P, IN1_N	2, 3	3, 4	I	Note that INP0, INN0 are used indistinguishably with IN0_P, IN0_N.
BANK ENABLE
EN	1	2	I	Output bank enable/disable with an internal 500-kΩ pullup and 320-kΩ pulldown. See Table 8-2.
AMPLITUDE SELECT
AMP_SEL	10	11	I	Output amplitude swing select with an internal 500-kΩ pullup and 320-kΩ pulldown. See Table 8-3.
BIAS VOLTAGE OUTPUT
V_{AC_REF0},V_{AC_REF1}	7, 4	8, 5	O	Bias voltage output for capacitive coupled inputs. If used, TI recommends using a 0.1-µF capacitor to GND on this pin.
DIFFERENTIAL CLOCK OUTPUT
OUT0_P, OUT0_N	12, 13	14, 15	O	Differential LVDS output pair number 0
OUT1_P, OUT1_N	14, 15	16, 17	O	Differential LVDS output pair number 1
OUT2_P, OUT2_N	16, 17	18, 19	O	Differential LVDS output pair number 2
OUT3_P, OUT3_N	18, 19	20, 21	O	Differential LVDS output pair number 3
OUT4_P, OUT4_N	22, 23	22, 23	O	Differential LVDS output pair number 4
OUT5_P, OUT5_N	24, 25	25, 26	O	Differential LVDS output pair number 5
OUT6_P, OUT6_N	26, 27	27, 28	O	Differential LVDS output pair number 6
OUT7_P, OUT7_N	28, 29	29, 30	O	Differential LVDS output pair number 7
OUT8_P, OUT8_N	32, 33	31, 32	O	Differential LVDS output pair number 8
OUT9_P, OUT9_N	34, 35	33, 34	O	Differential LVDS output pair number 9
OUT10_P, OUT10_N	36, 37	35, 36	O	Differential LVDS output pair number 10
OUT11_P, OUT11_N	38, 39	38, 39	O	Differential LVDS output pair number 11
OUT12_P, OUT12_N	—	40, 41	O	Differential LVDS output pair number 12
OUT13_P, OUT13_N	—	42, 43	O	Differential LVDS output pair number 13
OUT14_P, OUT14_N	—	44, 45	O	Differential LVDS output pair number 14
OUT15_P, OUT15_N	—	46, 47	O	Differential LVDS output pair number 15
SUPPLY VOLTAGE
V_DDA	6, 11, 20	7, 13, 24	P	Device power supply (1.8 V, 2.5 V, or 3.3 V) for Bank 0
V_DDB	5, 31, 40	6, 37, 48	P	Device power supply (1.8 V, 2.5 V, or 3.3 V) for Bank 1
GROUND
GND	21, 30	1, 12	G	Ground
MISC
DAP	DAP	DAP	G	Die Attach Pad. Connect to the printed circuit board (PCB) ground plane for heat dissipation.

(1) G = Ground, I = Input, O = Output, P = Power