The LMK1D210x is a low additive jitter LVDS fan-out buffer that can generate up to 6 (LMK1D2106) or 8 (LMK1D2108) LVDS copies of a single input that is either LVDS, LVPECL, HCSL, CML, or LVCMOS on each of its banks. The device has two banks, therefore this translates to a total of 12 (LMK1D2106) or 16 (LMK1D2108) pairs of outputs. Refer to the Table 8-1 for output bank mapping. The reference clock frequencies can go up to 2 GHz.

Apart from providing a very low additive jitter and low output skew, the LMK1D210x has an output bank enable/disable control pin (EN) and an output amplitude control pin (AMP_SEL).