APLL1 has no VCO post-dividers. The primary VCO1 clock (P1) and a secondary VCO1 inverted clock (P2) are distributed to all output channel muxes. The inverted clock is optional, but it can help reduce spurious outputs in some cases.

APLL2 has two VCO2 post-dividers to provide more flexible clock frequency planning. The primary VCO2 post-divider clock (P1) and secondary post-divider clock (P2) are distributed to all output channel muxes. Both VCO2 post-dividers support independently programmable dividers (÷2 to ÷7). Note that output SYNC is not supported between output channels selecting a VCO2 post-divider of 2.

TI recommends a PLL2 or device soft-reset after changing the APLL2 post-divider value to initialize it for deterministic divider operation.