Each output driver can automatically mute or squelch its clock when the selected output mux clock source is invalid, as configured by its CHx_MUTE bit. The source can be invalid based on the LOL status of each PLL by configuring the APLL and DPLL mute control bits (MUTE_APLLx_LOCK, MUTE_DPLL_LOCK, MUTE_DPLL_PHLOCK). The mute level can be configured per output channel by its CHx_MUTE_LVL bits, where the mute level depends on the configured output driver type (Differential/HCSL or LVCMOS). The mute level for a differential or HCSL driver can be set to output common mode, differential high, or differential low levels. The mute level for an LVCMOS driver pair can be set to output low level for each of its outputs (P and N) independently. When auto-mute is disabled or bypassed (CHx_MUTE = 0 and CHx_MUTE_LVL = 0), the output clock can have incorrect frequency or be unstable before and during the VCO calibration. For this reason, the mute bypass mode should only be used for diagnostic or debug purposes.