If some VDD core supplies are driven from different supply rails, TI recommends to start the PLL calibration after all of the core supplies have ramped above 3.135 V. This can be realized by delaying the PDN low-to-high transition. The PDN input incorporates a 200-kΩ resistor to VDD_IN and as shown in Figure 10-3, a capacitor from the PDN pin to GND can be used to form an R-C time constant with the internal pullup resistor. This R-C time constant can be designed to delay the low-to-high transition of PDN until all the core supplies have ramped above 3.135 V.

Alternatively, the PDN pin can be driven high by a system host or power management device to delay the device power-up sequence until all VDD supplies have ramped.

Figure 10-3 Recommendation for Power Up From Split-Supply Rails