The DPLL constantly monitors its reference inputs for a valid input clock. When at least one valid input clock is detected, the PLL1 channel will exit free-run mode or holdover mode and initiate lock acquisition through the DPLL. The device supports the Fastlock feature where the DPLL temporarily engages a wider loop bandwidth to reduce the lock time. Once the lock acquisition is done, the loop bandwidth is set to its normal configured loop bandwidth setting (BW_DPLL).