ZHCSLM0A May   2020  – January 2021 LMK5B12204

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
    1. 6.1 Device Start-Up Modes
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: 4-Layer JEDEC Standard PCB
    5. 7.5 Thermal Information: 10-Layer Custom PCB
    6. 7.6 Electrical Characteristics
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Output Clock Test Configurations
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 ITU-T G.8262 (SyncE) Standards Compliance
    2. 9.2 Functional Block Diagram
      1. 9.2.1 PLL Architecture Overview
      2. 9.2.2 DPLL Mode
      3. 9.2.3 APLL-Only Mode
    3. 9.3 Feature Description
      1. 9.3.1  Oscillator Input (XO_P/N)
      2. 9.3.2  Reference Inputs (PRIREF_P/N and SECREF_P/N)
        1. 9.3.2.1 Programmable Input Hysteresis
      3. 9.3.3  Clock Input Interfacing and Termination
      4. 9.3.4  Reference Input Mux Selection
        1. 9.3.4.1 Automatic Input Selection
        2. 9.3.4.2 Manual Input Selection
      5. 9.3.5  Hitless Switching
        1. 9.3.5.1 Hitless Switching With 1-PPS Inputs
      6. 9.3.6  Gapped Clock Support on Reference Inputs
      7. 9.3.7  Input Clock and PLL Monitoring, Status, and Interrupts
        1. 9.3.7.1 XO Input Monitoring
        2. 9.3.7.2 Reference Input Monitoring
          1. 9.3.7.2.1 Reference Validation Timer
          2. 9.3.7.2.2 Amplitude Monitor
          3. 9.3.7.2.3 Frequency Monitoring
          4. 9.3.7.2.4 Missing Pulse Monitor (Late Detect)
          5. 9.3.7.2.5 Runt Pulse Monitor (Early Detect)
          6. 9.3.7.2.6 Phase Valid Monitor for 1-PPS Inputs
        3. 9.3.7.3 PLL Lock Detectors
        4. 9.3.7.4 Tuning Word History
        5. 9.3.7.5 Status Outputs
        6. 9.3.7.6 Interrupt
      8. 9.3.8  PLL Relationships
        1. 9.3.8.1  PLL Frequency Relationships
        2. 9.3.8.2  Analog PLLs (APLL1, APLL2)
        3. 9.3.8.3  APLL Reference Paths
          1. 9.3.8.3.1 APLL XO Doubler
          2. 9.3.8.3.2 APLL1 XO Reference (R) Divider
          3. 9.3.8.3.3 APLL2 Reference (R) Dividers
        4. 9.3.8.4  APLL Phase Frequency Detector (PFD) and Charge Pump
        5. 9.3.8.5  APLL Feedback Divider Paths
          1. 9.3.8.5.1 APLL1 N Divider With SDM
          2. 9.3.8.5.2 APLL2 N Divider With SDM
        6. 9.3.8.6  APLL Loop Filters (LF1, LF2)
        7. 9.3.8.7  APLL Voltage Controlled Oscillators (VCO1, VCO2)
          1. 9.3.8.7.1 VCO Calibration
        8. 9.3.8.8  APLL VCO Clock Distribution Paths (P1, P2)
        9. 9.3.8.9  DPLL Reference (R) Divider Paths
        10. 9.3.8.10 DPLL Time-to-Digital Converter (TDC)
        11. 9.3.8.11 DPLL Loop Filter (DLF)
        12. 9.3.8.12 DPLL Feedback (FB) Divider Path
      9. 9.3.9  Output Clock Distribution
      10. 9.3.10 Output Channel Muxes
      11. 9.3.11 Output Dividers (OD)
      12. 9.3.12 Clock Outputs (OUTx_P/N)
        1. 9.3.12.1 AC-Differential Output (AC-DIFF)
        2. 9.3.12.2 HCSL Output
        3. 9.3.12.3 1.8-V LVCMOS Output
        4. 9.3.12.4 Output Auto-Mute During LOL
      13. 9.3.13 Glitchless Output Clock Start-Up
      14. 9.3.14 Clock Output Interfacing and Termination
      15. 9.3.15 Output Synchronization (SYNC)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Start-Up Modes
        1. 9.4.1.1 EEPROM Mode
        2. 9.4.1.2 ROM Mode
      2. 9.4.2 PLL Operating Modes
        1. 9.4.2.1 Free-Run Mode
        2. 9.4.2.2 Lock Acquisition
        3. 9.4.2.3 Locked Mode
        4. 9.4.2.4 Holdover Mode
      3. 9.4.3 PLL Start-Up Sequence
      4. 9.4.4 Digitally-Controlled Oscillator (DCO) Mode
        1. 9.4.4.1 DCO Frequency Step Size
        2. 9.4.4.2 DCO Direct-Write Mode
    5. 9.5 Programming
      1. 9.5.1 Interface and Control
      2. 9.5.2 I2C Serial Interface
        1. 9.5.2.1 I2C Block Register Transfers
      3. 9.5.3 SPI Serial Interface
        1. 9.5.3.1 SPI Block Register Transfer
      4. 9.5.4 Register Map and EEPROM Map Generation
      5. 9.5.5 General Register Programming Sequence
      6. 9.5.6 EEPROM Programming Flow
        1. 9.5.6.1 EEPROM Programming Using Method #1 (Register Commit)
          1. 9.5.6.1.1 Write SRAM Using Register Commit
          2. 9.5.6.1.2 Program EEPROM
        2. 9.5.6.2 EEPROM Programming Using Method #2 (Direct Writes)
          1. 9.5.6.2.1 Write SRAM Using Direct Writes
          2. 9.5.6.2.2 User-Programmable Fields In EEPROM
      7. 9.5.7 Read SRAM
      8. 9.5.8 Read EEPROM
      9. 9.5.9 EEPROM Start-Up Mode Default Configuration
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Device Start-Up Sequence
      2. 10.1.2 Power Down (PDN) Pin
      3. 10.1.3 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 10.1.3.1 Mixing Supplies
        2. 10.1.3.2 Power-On Reset (POR) Circuit
        3. 10.1.3.3 Powering Up From a Single-Supply Rail
        4. 10.1.3.4 Power Up From Split-Supply Rails
        5. 10.1.3.5 Non-Monotonic or Slow Power-Up Supply Ramp
      4. 10.1.4 Slow or Delayed XO Start-Up
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Bypassing
    2. 11.2 Device Current and Power Consumption
      1. 11.2.1 Current Consumption Calculations
      2. 11.2.2 Power Consumption Calculations
      3. 11.2.3 Example
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Reliability
      1. 12.3.1 Support for PCB Temperature up to 105 °C
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 TICS Pro
      2. 13.1.2 Related Documentation
    2. 13.2 接收文档更新通知
    3. 13.3 支持资源
    4. 13.4 Trademarks
    5. 13.5 静电放电警告
    6. 13.6 术语表
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Package Option Addendum
      1. 14.1.1 Packaging Information
      2. 14.1.2 Tape and Reel Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

GUID-13AFADEC-D2EB-4ECB-B7F1-102C37AD9B1F-low.gif Figure 6-1 RGZ Package48-Pin VQFNTop View
Table 6-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
POWER
GND PAD G Ground / Thermal Pad.
The exposed pad must be connected to PCB ground for proper electrical and thermal performance. A 5×5 via pattern is recommended to connect the IC ground pad to the PCB ground layers.
VDD_IN 5 P Core Supply (3.3 V) for Primary and Secondary Reference Inputs.
Place a nearby 0.1-µF bypass capacitor on each pin.
VDD_XO 33 P Core Supply (3.3 V) for XO Input.
Place a nearby 0.1-µF bypass capacitor on each pin.
VDD_PLL1 27 P Core Supply (3.3 V) for PLL1, PLL2, and Digital Blocks.
Place a nearby 0.1-µF bypass capacitor on each pin.
VDD_PLL2 36 P
VDD_DIG 4 P
VDDO_0 18 P Output Supply (1.8, 2.5, or 3.3 V) for Clock Outputs 0 to 3.
Place a nearby 0.1-µF bypass capacitor on each pin.
VDDO_1 19 P
VDDO_2 37, 40 P
VDDO_3 43, 46 P
CORE BLOCKS
LF1 29 A External Loop Filter Capacitor for APLL1 and APLL2.
Place a nearby capacitor on each pin. For LF1, a 0.47-µF capacitor is suggested for typical APLL1 loop bandwidths around 1.0 kHz. For LF2, a 0.1-µF capacitor is suggested for typical APLL2 loop bandwidth around 500 kHz.
LF2 34 A
CAP_PLL1 28 A External Bypass Capacitors for APLL1, APLL2, and Digital Blocks.
Place a nearby 10-µF bypass capacitor on each pin.
CAP_PLL2 35 A
CAP_DIG 3 A
INPUT BLOCKS
PRIREF_P 6 I DPLL Primary and Secondary Reference Clock Inputs.
Each input pair can accept a differential or single-ended clock as a reference to the DPLL. Each pair has a programmable input type with internal termination to support AC- or DC-coupled clocks. A single-ended LVCMOS clock can be applied to the P input with the N input pulled down to ground. An unused input pair can be left floating.

For low-frequency input, an internal AC-coupling capacitor can be disabled to improve noise immunity. Differential Input and LVCMOS input can be DC-coupled to the receiver.
PRIREF_N 7 I
SECREF_P 10 I
SECREF_N 11 I
XO_P 31 I XO/TCXO/OCXO Input.
This input pair can accept a differential or single-ended clock signal from a low-jitter local oscillator as a reference to the APLLs. This input has a programmable input type with internal termination to support AC- or DC-coupled clocks. A single-ended LVCMOS clock (up to 2.5 V) can be applied to the P input with the N input pulled down to ground. A low-frequency TCXO or OCXO can be used to set the clock output frequency accuracy and stability during free-run and holdover modes.
In DPLL mode, the XO frequency must have a non-integer relationship to the VCO1 frequency so APLL1 can operate in fractional mode (required for proper DPLL operation). In APLL-only mode, the XO frequency can have either an integer or non-integer relationship to the VCO1 frequency.
XO_N 32 I
OUTPUT BLOCKS
OUT0_P 17 O Clock Outputs 0 and 1 Bank.
Each programmable output driver pair can support AC-LVDS, AC-CML, AC-LVPECL, and HCSL. Unused differential outputs should be terminated if active or left floating if disabled through registers.
The OUT[0:1] bank is preferred for PLL1 clocks to minimize output crosstalk.
OUT0_N 16 O
OUT1_P 20 O
OUT1_N 21 O
OUT2_P 42 O Clock Outputs 2 and 3 Bank.
Each programmable output driver pair can support AC-LVDS, AC-CML, AC-LVPECL, HCSL, or 1.8-V LVCMOS clocks (one or two per pair). Unused differential outputs should be terminated if active or left floating if disabled through registers.
The OUT[2:3] bank is preferred for PLL2 clocks to minimize output crosstalk. When PLL2 is not used, the OUT[2:3] bank can be used for PLL1 clocks without risk of cross-coupling from PLL2.
OUT2_N 41 O
OUT3_P 45 O
OUT3_N 44 O
LOGIC CONTROL / STATUS (2)(3)
HW_SW_CTRL 9 I Device Start-Up Mode Select (3-level, 1.8-V compatible).
This input selects the device start-up mode that determines the memory page used to initialize the registers, serial interface, and logic pin functions. The input level is sampled only at device power-on reset (POR).
See Table 6-2 for start-up mode descriptions and logic pin functions.
PDN 13 I Device Power-Down (active low).
When PDN is pulled low, the device is in hard-reset and all blocks including the serial interface are powered down. When PDN is pulled high, the device is started according to device mode selected by HW_SW_CTRL and begins normal operation with all internal circuits reset to their initial state.
SDA/SDI 25 I/O I2C Serial Data I/O (SDA) or SPI Serial Data Input (SDI). See Table 6-2.
When HW_SW_CTRL is 0 or 1, the serial interface is I2C. SDA and SCL pins (open-drain) require external I2C pullup resistors. The default 7-bit I2C address is 11001xxb, where the MSB bits (11001b) are initialized from on-chip EEPROM and the LSB bits (xxb) are determined by the logic input pins. When HW_SW_CTRL is 0, the LSBs are determined by the GPIO1 input state (3-level) during POR. When HW_SW_CTRL is 1, the LSBs are fixed to 00b.
When HW_SW_CTRL is Float, the serial interface is SPI (4-wire, Mode 0) using the SDI, SCK, SCS, and SDO pins.
SCL/SCK 26 I I2C Serial Clock Input (SCL) or SPI Serial Clock Input (SCK). See Table 6-2.
GPIO0/SYNCN 12 I Multifunction Inputs or Outputs.
See Table 6-2.
GPIO1/SCS 24 I
GPIO2/SDO/
FINC		 30 I/O
STATUS0 1 I/O Status Outputs 0 and 1.
Each output has programmable status signal selection, driver type (3.3-V LVCMOS or open-drain), and status polarity. Open-drain requires an external pullup resistor. Leave pin floating if unused.
In I2C mode, the STATUS1/FDEC pin can function as a DCO mode control input pin. See Table 6-2.
STATUS1/
FDEC		 2 I/O
REFSEL 8 I Manual DPLL Reference Clock Input Selection. (3-level, 1.8-V compatible).
REFSEL = 0 (PRIREF), 1 (SECREF), or Float or VIM (Auto Select). This control pin must be enabled by register default or programming. Leave pin floating if unused.
(1) G = Ground, P = Power, I = Input, O = Output, I/O = Input or Output, A = Analog.
(2) Internal resistors: PDN pin has 200-kΩ pullup to VDD_IN. HW_SW_CTRL, GPIO, REFSEL, and STATUS pins each have a 150-kΩ bias to VIM (approximately 0.8 V) when PDN = 0 or 400-kΩ pulldown when PDN = 1.
(3) Unless otherwise noted: Logic inputs are 2-level, 1.8-V compatible inputs. Logic outputs are 3.3-V LVCMOS levels.
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |