To support the IEEE 1588 slave clock and other clock steering applications, the DPLL supports DCO mode to allow precise output clock frequency adjustment of less than 0.001 ppb/step. DCO mode can be enabled (DPLL_FDEV_EN = 1) when the DPLL is locked.

The DCO frequency step size can be programmed through a 38-bit frequency deviation word register (DPLL_FDEV bits). The DPLL_FDEV value is an offset added to or subtracted from the current numerator value of the DPLL fractional feedback divider and determines the DCO frequency offset at the VCO output.

The DCO frequency increment (FINC) or frequency decrement (FDEC) updates can be controlled through software control or pin control in I²C mode. DCO updates through software control are always available through I²C or SPI by writing to the DPLL_FDEV_REG_UPDATE register bit. Writing a 0 will increment the DCO frequency by the programmed step size, and writing a 1 will decrement it by the step size. SPI can achieve faster DCO update rates than to I²C because the SPI has faster register transfer.

When pin control mode is enabled (GPIO_FDEV_EN = 1) in I²C mode, the GPIO2/SDO/FINC pin will function as the FINC input and the STATUS1/FDEC pin will function as the FDEC input (STATUS1 output will be disabled). A positive pulse on the FINC pin or FDEC pin will apply a corresponding DCO update to the DPLL. The minimum positive pulse width applied to the FINC or FDEC pins should be greater than 100 ns to be captured by the internal sampling clock. The DCO update rate should be limited to less than 1 MHz when using pin control.

When DCO mode is disabled (DPLL_FDEV_EN = 0), the DCO frequency offset will be cleared and the VCO output frequency will be determined by the original numerator value of the DPLL fractional feedback divider.

Figure 9-34 DCO Mode Control Options