For the DPLL block, the reference input mux selection can be done automatically using an internal state machine with a configurable input priority scheme, or manually through software register control or hardware pin control. The input mux can select IN0 or IN1 for LMK5B33216. The priority for all inputs can be assigned through registers. The priority ranges from 0 to 7, where 0 = ignore (never select), 1 = first priority, 2 = second priority and 7 = 7th priority. When all inputs are configured with the same priority setting, IN0 will be given first priority (IN0 → IN1). The selected input can be monitored through the status pins or register.