Figure 8-37 shows the general sequence for PLL start-up after device configuration. This sequence also applies after a device soft-reset or individual PLL soft-reset. To ensure proper VCO calibration, it is critical for the external XO clock to be stable in amplitude and frequency prior to the start of VCO calibration otherwise the VCO calibration can fail and prevent start-up of the PLL and its output clocks.

Also see Figure 8-14, Figure 8-35, and Figure 8-36.