The phase valid monitor is designed specifically for 1-PPS input validation because the frequency and window detectors do not support this low frequency. The phase valid monitor uses a window detector to validate 1-PPS input pulses that arrive within the nominal clock period (T_IN) plus a programmable jitter threshold (T_JIT). When the input pulse arrives within the counter window (T_V), the pulse is considered valid and the phase valid flag is cleared. When the input pulse does not arrive before T_V (due to a missing or late pulse), the flag is set immediately to disqualify the input. T_JIT should be set higher than the worst-case input cycle-to-cycle jitter.

The phase valid register settings also are valid for 1-PPS ppm error threshold detect. Notice the T_JIT also impacts the worst case ppm error allowed. For example: High_Jitter_Freq = 1/(T_IN - T_JIT), then Max input allowable ppm error = (High_Jitter_Freq - Expected_Freq) / Expected_Freq × 1e6.

Figure 8-17 1-PPS Input Window Detector Example