Zero-delay mode synchronization can be enabled to achieve zero phase delay between the selected DPLL reference input clock and the selected zero-delay feedback clock. Figure 8-29 shows how the OUT0 clock can feedback to any DPLL for zero-delay. Zero-delay mode is primarily implemented to achieve deterministic phase relationship between an input and some outputs, for example, 1-PPS input and 1-PPS output.

In addition to OUT0, for DPLL2, OUT4 may be used for ZDM. For DPLL3, OUT10 may be used for ZDM.

1-PPS phase alignment is able to re-establish with the phase slew control and ZDM. For 1-PPS and ZDM, hitless switching must be enabled to prevent the DPLL from becoming unlocked. After preforming hitless switching, the phase slew control can reduce the phase build out back to 0 at a controlled rate. Input to output phase error is user programmable using the DPLLx_PH_OFFSET field. To lock to a 1-PPS signal using ZDM mode, the output static delay or DPLLx_PH_OFFSET must be programmed to zero out the phase error between the 1 PPS input and 1 PPS feedback clock.