Figure 8-2 shows the PLL architecture implemented in the LMK5B33216. The ultra-low jitter channel consists of a digital PLL (DPLL3) and analog PLL (APLL3) with integrated BAW VBCO (VCO3). APLL2 with integrated LC VCO (VCO2) can generate another additional low jitter clock domain. APLL2's feedback N divider numerator can be controlled by DPLL2. APLL1 with integrated LC VCO (VCO1) can be used as a clock generation domain. APLL1's feedback N divider numerator can be controlled by DPLL1.

The DPLL is comprised of a time-to-digital converter (TDC), digital loop filter (DLF), and programmable 40-bit fractional feedback (FB) divider with sigma-delta-modulator (SDM). The APLLs are comprised of a reference (R) divider, phase-frequency detector (PFD), loop filter (LF), fractional feedback (N) divider with SDM, and VCO.

Each DPLL has a reference selection mux that allows the DPLL to be either locked to any reference input or another APLL's cascade divider output. TI's cascading architecture provides unique flexibility for hybrid synchronization of frequency and phase control across multiple clock domains.

Each APLL has a reference selection mux that allows the APLL to be either locked to the XO input, or another APLL's cascade divider output.

Each APLL has a fixed 40-bit denominator controllable by the DPLL when locked to an input reference. When one or more of the APLL are operating without DPLL control in APLL only mode, a programmable 24-bit denominator is also available for selection to synthesize exact frequency ratios. TI recommends the programmable 24-bit denominator when implementing hybrid synchronization or cascading between frequency domains in order to maintain 0 ppm frequency error without DPLL control.

Do not cascade one VCO output to both the DPLL reference and APLL reference of the same DPLL/APLL pair.

Any unused DPLL or APLL should be disabled (powered-down) to save power. Each APLL's VCO drives the clock distribution blocks through their respective VCO post-dividers. If the post-divider setting is 1 for VCO3, the post-divider is bypassed and VCO3 feeds the output clock distribution blocks directly.

The following sections describe the basic principles of DPLL and APLL operation. See Section 8.4.2 for more details on the PLL modes of operation including holdover.