DCO mode can be enabled (DPLLx_FB_FDEV_EN = 1) when the DPLL is locked.

There are three methods to steer frequency when using the DPLL DCO.

• Register relative adjustment
  • Preset the deviation amount in DPLL_FDEV
  • Write an 8-bit register to enable increment/decrement by the deviation amount
• GPIO relative adjustment
  • Step/Direction GPIOx trigger
  • Adjust DPLLx_FB_NUM by programming a deviation amount for each step in pin set direction.
• Register absolute adjustment
  • Write the DPLLx_FB_NUM [39:0] based on the frequency control word (FCW)

The DCO frequency step size can be programmed through a 38-bit frequency deviation word register (DPLL_FDEV bits). The DPLL_FDEV value is an offset added to or subtracted from the current numerator value of the DPLL fractional feedback divider and determines the DCO frequency offset at the VCO output.

The DCO frequency increment (FINC) or frequency decrement (FDEC) updates can be controlled through software control (DPLLx_FB_FDEV_UPDATE) or user selectable pin control (GPIOx). DCO updates through software control are always available through I²C or SPI by writing to the DPLLx_FB_FDEV_UPDATE register bit. Writing a 0 will increment the DCO frequency by the programmed step size, and writing a 1 will decrement the DCO frequency by the step size. SPI can achieve faster DCO update rates than I²C because the SPI has faster write speed.

When DPLL pin control is selected (FDEV_TRIG_DPLLx and FDEV_DIR_DPLLx on GPIOs), a rising edge on the GPIO pin defined in FDEV_TRIG_DPLLx will apply a corresponding DCO update to the DPLL, another GPIO defined in FDEV_DIR_DPLLx will determine the direction of the FDEV trigger. FDEV_DIR_DPLLx = 0 means positive, FDEV_DIR_DPLLx = 1 means negative. In this way, the GPIO pins will function as the FINC or FDEC input. The minimum positive pulse width applied to the trigger pins should be greater than 100 ns to be captured by the internal sampling clock. The DCO update rate should be limited to less than 5 MHz when using pin control.

When DCO control is disabled (DPLLx_FB_FDEV_EN = 0), the DCO frequency offset will be cleared and the VCO output frequency will be determined by the original numerator value of the DPLL fractional feedback divider.