The following equations provide the APLL and DLL frequency relationships required to achieve closed-loop operation. The TICS Pro programming software can be used to generate valid divider settings based on the desired frequency plan.

Note that any divider in the following equations refers to the actual divide value (or range) and not its programmable register value.

When DPLL operation is enabled, the calculated DPLL frequency and APLL frequency must be nominally the same. The DPLL adjustments to the paired APLL N divider 40-bit fixed denominator will track the selected input reference source to synthesize the actual clock output desired frequency and phase.

When the APLL operates independently from its paired DPLL, TI recommends the programmable 24-bit denominator for hybrid synchronization or cascading between frequency domains in order to maintain 0 ppm frequency error without DPLL control. In this scenario the APLL will which track the cascade feedback divider reference from another APLL output.

When using ZDM (zero delay mode) for a PLL, the clock output divider must be accounted for in the VCO frequency calculations.