Users may write to the DPLLx_PH_OFFSET[44:0] register fields to adjust the DPLL phase offset. The phase offset is a signed 2-s complement value with a default setting of 0 and offsets the phase relationship of the feedback clock to reference clock at the TDC. The phase adjustment is common to all outputs derived from the DPLLx synchronization domain.

Equation 13 shows the formula to compute the DPLLx_PH_OFFSET field value to vary the output phase in fine adjustment steps. DPLLx_PH_OFFSET is related to the APLLx VCO period with a scaling factor for decimation and digital gain.

where

• DPLLx_PH_OFFSET: Programmable register value adjusting DPLL output phase
• Desired_Phase_Offset: Desired DPLL phase adjustment step size (in seconds)
• f_VCOx: VCOx frequency
• SCALING_DEC: Scaling factor accounting for decimation and digital gain components (2 +1) × 958 = 2874

For example, if the user wants to introduce a phase offset of 38.5 ps into the DPLL3/APLL3 synchronization domain

• Desired_Phase_Offset = 38.5 ps
• f_VCOx: = 2500 MHz
• SCALING_DEC = 2874
• DPLL_PH_OFFSET = 38.5e-12 × 2500e6 × 2 x 2874 = 558