Because the external XO clock input is used as the reference input for the APLL1/VCO1 and APLL2/VCO2 calibration, the XO input amplitude and frequency must be stable before the start of VCO calibration to ensure successful PLL lock and output start-up. If the XO clock is not stable prior to VCO calibration, the VCO calibration can fail and prevent PLL lock and output clock start-up.

If the XO clock has a slow start-up time or has glitches on power-up (due to a slow or non-monotonic power supply ramp, for example), TI recommends to delay the start of VCO calibration until after the XO is stable. This could be achieved by delaying the PD# low-to-high transition until after the XO clock has stabilized using one of the methods described in Section 9.1.6.3. It is also possible to issue a device soft-reset after the XO clock has stabilized to manually trigger the VCO calibration and PLL start-up sequence.

APLL3/VCO3 is factory calibrated and is not sensitive to an invalid XO reference start-up. Upon valid XO reference, APLL3/VCO3 will be able to acquire lock. When APLL3/VCO3 is used in conjunction with DPLL3, it is necessary for the XO to be valid before a DPLL3 reference is validated.