Each clock output can be individually configured as a differential driver (AC-LVPECL/HSDS/LVDS/HCSL). The HSDS driver has the capability to program output voltage swing and common mode voltage. Unused clock outputs can be disabled to save power.

Each output channel has its own internal LDO regulator to provide excellent PSNR and minimize jitter and spurs induced by supply noise. For differential modes, the output clock specifications (such as output swing, phase noise, and jitter) are not sensitive to the VDDO_x voltage because of the channel's internal LDO regulator.

The OUT0 and OUT1 channel (mux, divider, and drivers) are powered through a single output supply pin (VDDO_0_1), and similarly for the OUT2 and OUT3 channel (VDDO_2_3). Output banks OUT4 to OUT7 and OUT8 to OUT13 each have their own output supply pin (VDDO_4_TO_7) and (VDDO_8_TO_13) respectively. Each output supply pin should be powered by 3.3-V and always connected to the supply even if not used.

OUT0 or OUT1 has the additional capability for two 1.8-V or 2.65-V LVCMOS drivers per output pair. CMOS output voltage levels are determined by internal programming of the CMOS output LDO to support either 1.8-V or 2.65-V LVCMOS.

For additional low frequency single ended clock outputs GPIO1 and GPIO2 may be configured to replicate any 1PPS/SYSREF divider output from another differential output pair.