Each APLL has a post divider which will provide a
VCO post divider frequency calculated in Equation 6, Equation 7, or Equation 8. The final output
frequency is calculated by dividing from the VCO post divider frequency and the output
divide (see Equation 9). For each output, the
output frequency depends on the selected APLL clock source and output divider value.
Equation 6. APLL1 selected: fPOST_DIV =
fVCO1 / PnAPLL1
Equation 7. APLL2 selected: fPOST_DIV =
fVCO2 / P1APLL2
Equation 8. APLL3 selected: fPOST_DIV =
fVCO3 / P1APLL3
Equation 9. OUT[0:15]: fOUTx = fPOST_DIV / ODOUTx
where
- fPOST_DIV: Output mux source frequency (APLL1, APLL2 or APLL3 post-divider clock)
- PnAPLL1: APLL1 primary P1 or secondary
P2 post-divide value (2 to 7)
- P1APLL2: APLL2 primary P1 post-divide
value (2 to 13)
- P1APLL3: APLL3 post-divide value =
div8 (2 to 8) , div8 times 2 (10, 12, 14, 16) , or bypass
(1)
- fOUTx: Output clock frequency (x = 0 to 15)
- ODOUTx: OUTx output bypass or divider value. All outputs have a
12-bit divider with values 1 to (212 – 1). All outputs except OUT2 and OUT3
have the option to follow the 12-bit divider with a 20-bit SYSREF divider that can be used
to produce 1-PPS or other frequencies below 1 Hz when the SYSREF output is set for
continuous output.