When SPI control interface is selected, the device uses a 3-wire SPI interface with SDIO, SCK, and SCS signals (SPI_3WIRE_DIS = 0). When using SPI interface SCS_ADD also can act as a Time Elapsed Counter (TEC) trigger. When set SPI_3WIRE_DIS = 1, any GPIO may be selected as SDO to support readback with 4-wire SPI.

The host device must present data to the device MSB first. A message includes a transfer direction bit ( W/R), a 15-bit address field (A14 to A0), and a 8-bit data field (D7 to D0) as shown in Figure 8-43. The W/R bit is 0 for a SPI write and 1 for a SPI read.

Figure 8-43 SPI Message Format

A message frame is initiated by asserting SCS low. The frame ends when SCS is deasserted high. The first bit transferred is the W/R bit. The next 15 bits are the register address, and the remaining eight bits are data. On write transfers, data is committed in bytes as the final data bit (D0) is clocked in on the rising edge of SCK. If the write access is not an even multiple of eight clocks, the trailing data bits are not committed. On read transfers, data bits are clocked out from the SDO pin on the falling edges of SCK.