The device can also support APLL frequency and phase control through writing the 40-bit register DPLLx_FREE_RUN[39:0] while the DPLL is in holdover or not used. If the reference clock in a free-run mode or disabled, DPLL will disconnect with APLL, but users can still adjust frequency and phase accuracy.

To enable APLL DCO control, set DPLLx_LOOP_EN = 1, and PLLx_MODE = 1 for 40-bit fractional denominator. DPLLx_EN may be set = 0.

Figure 8-40 APLL DCO Mode

There are two alternative methods in adjusting the APLL DCO.

• Absolute frequency adjustment
  • Set DPLLx_HIST_EN = 0
  • Effective APLLx_NUM (APLLx_NUM_STAT) = APLLx_NUM + DPLLx_FREE_RUN
    • The APLLx_NUM_STAT is a read-only register and can be read back.
    • The DPLL loop filter block will modify the APLLx_NUM_STAT based on DPLLx_FREE_RUN value.
  • DPLLx_FREE_RUN is a 40-bit 2s complement number
• Relative frequency adjustment
  • Set DPLLx_HIST_EN = 1
  • DPLLx_FREE_RUN value is fed into the APLLx_NUM at a controlled rate defined by a step size register and step period register.
  • If another DPLLx_FREE_RUN write occurs before the LMK is complete in making the last adjustment, any remaining steps are lost and the new value begins to feed the APLL numerator.
  • A flag is set when the DPLLx_FREE_RUN word is fully fed into the effective APLLx_NUM (APLL_NUM_STAT).