In a typical application, TI recommends the following steps:
- Use the device GUI in the TICS Pro programming software for a step-by-step design flow to enter the design parameters, calculate the frequency plan for each PLL domain, and generate the register settings for the desired configuration. The register settings can be exported (registers hex dump in txt format) to enable host programming.
- A host device can program the register settings through the serial interface after power-up and issue a soft-reset (by SWRST bit) to start the device. Set SW_SYNC before, and clear after SWRST.
- Tie the GPIO1 pin to ground to select the I2C communications
interface, or pull up GPIO1 high to VDD_DIG through an external resistor to
select the SPI communications interface. Determine the logic I/O pin assignments
for control and status functions. See Figure 8-36.
- Connect I2C/SPI and logic I/O pins (1.8-V
compatible levels) to the host device pins with the proper I/O direction
and voltage levels.
- Select an XO frequency by following Section 8.3.1.
- Choose an XO with target phase jitter performance that
meets the frequency stability and accuracy requirements required for the
output clocks during free-run or holdover.
- For a 3.3-V LVCMOS
driver, LMK5B33414 can accept it directly. Power the XO
from a low-noise LDO regulator or optimize its power filtering to avoid
supply noise-induced jitter on the XO clock.
- TICS Pro: Configure the XO frequency to match
the XO port input.
- Wire the clock I/O for each APLL domain in the
schematic and use TICS Pro to configure the device settings as follows:
- Reference inputs: Follow the LVCMOS or
differential clock input interface examples in Figure 9-3 or Section 8.3.3.
- TICS Pro: For DPLL mode, configure the reference input
buffer modes to match the reference clock driver interface
requirements. See Section 8.3.2.
- TICS Pro: For DPLL mode, configure the DPLL
input selection modes and input priorities. See Section 8.3.4.
- TICS Pro: Configure each APLL reference from
other VCO domain (Cascaded mode) or XO clock (Non-cascaded mode).
- TICS Pro: Configure each output with the
required clock frequency and APLL domain. TICS Pro can calculate the VCO
frequencies and divider settings for the APLL and outputs. Consider the
following output clock assignment guidelines to minimize crosstalk and
spurs:
- OUT[0:1] bank can select any APLL clocks, XO,
and references.
- OUT[2:3] bank is preferred for APLL1 or APLL2
clocks.
- OUT[4:7] bank is preferred for APLL2 or APLL3
clocks.
- OUT[8:13] bank is preferred for APLL3 or APLL2
clocks.
- Group identical output frequencies
(or harmonic frequencies) on adjacent channels, and use the
output pairs with a single divider (for example, OUT2/3) when
possible to minimize power.
- Separate clock outputs when the difference of
the two frequencies, |fOUTx – fOUTy|,
falls within the jitter integration bandwidth (for example, 12
kHz to 20 MHz). Any outputs that are potential aggressors should
be separated by at least four static pins (power pin, logic pin,
or disabled output pins) to minimize potential coupling. If
possible, separate these clocks by the placing them on opposite
output banks, which are on opposite sides of the chip for best
isolation.
- Avoid or isolate any LVCMOS output (strong
aggressor) from other jitter-sensitive differential output
clocks. If an LVCMOS output is required, use dual complementary
LVCMOS mode (+/- or -/+) with the unused LVCMOS output left
floating with no trace.
- If not all outputs pairs are used in the
application, consider connecting an unused output to a pair of
RF coaxial test structures for testing purposes (such as SMA,
SMP ports).
- TICS Pro: Configure the output drivers.
- Configure the output driver modes to match the
receiver clock input interface requirements. See Section 8.3.14.
- Configure any output SYNC groups that need
their output phases synchronized. See Section 8.3.17.
- Configure the output auto-mute modes, and APLL
and DPLL mute options. See Section 8.3.14.4.
- Clock output Interfacing: Follow the
single-ended or differential clock output interface examples in Figure 9-3 or Section 8.3.16.
- Differential
outputs can be AC-coupled and terminated and biased at the
receiver inputs, or DC-coupled with proper receivers
- LVCMOS outputs
have internal source termination to drive 50-Ω traces directly.
LVCMOS VOH level is determined by internal LDO
programmed voltage (1.8 V or 2.65 V).
- TICS Pro: Configure the DPLL loop bandwidth.
- Below the loop bandwidth, the reference noise
is added to the TDC noise floor and the XO/TCXO/OCXO noise.
Above the loop bandwidth, the reference noise will be attenuated
with roll-off up to 60 dB/decade. The optimal bandwidth depends
on the relative phase noise between the reference input and the
XO. APLL's loop bandwidth can be configured to provide
additional attenuation of the reference input, TDC, and XO phase
noise above APLL's bandwidth.
- TICS Pro: Configure the maximum TDC frequency
to optimize the DPLL TDC noise contribution for the desired use case.
- Wired: A 400 kHz maximum TDC rate is
commonly specified. This supports SyncE and other use cases
using a narrow loop bandwidth (≤10 Hz) with a TCXO/OCXO/XO to
set the frequency stability and wander performance.
- Wireless: A 26 MHz maximum TDC rate is
commonly specified for lowest in-band TDC noise contribution.
This supports wireless and other use cases where close-in phase
noise is critical.
- TICS Pro: If clock steering is needed (such as
for IEEE 1588 PTP), enable DCO mode for the DPLL loop and enter the
frequency step size (in ppb). The FDEV step register will be computed
according to Section 8.4.4.1.2. Enable the FDEV_TRIG and FDEV_DIR pin control on the GPIO
pins if needed.
- TICS Pro: If deterministic input-to-output
clock phase is needed, enable the ZDM as required on OUT0, OUT4, or
OUT10. See Section 8.3.18.
- TICS Pro: Configure the reference input monitoring options for each
reference input. Disable the monitor when not required or when the input
operates beyond the monitor's supported frequency range. See Section 8.3.7.2.
- Frequency monitor: Set the valid and invalid
thresholds (in ppm).
- Missing pulse monitor: Set the late window
threshold (TLATE) to allow for the longest expected input
clock period, including worst-case cycle-to-cycle jitter. For a gapped
clock input, set TLATE based on the number of allowable
missing clock pulses.
- Runt pulse monitor: Set the early window
threshold (TEARLY) to allow for the shortest expected input
clock period, including worst-case cycle-to-cycle jitter.
- 1-PPS Phase validation monitor: Set the phase
validation jitter threshold, including worst-case input cycle-to-cycle
jitter.
- Validation timer: Set the amount of time the
reference input must be qualified by all enabled input monitors before
the input is valid for selection.
- TICS Pro: Configure the DPLL lock detect and tuning word history
monitoring options for each channel. See Section 8.3.7.3 and Section 8.3.7.4.
- DPLL frequency lock and phase lock detectors:
Set the lock and unlock thresholds for each detector.
- TICS Pro: Configure each status output pin and interrupt flag as
needed. See Section 8.3.7.5 and Section 8.3.7.6.
- Select the desired status signal selection, status
polarity, and driver mode (3.3-V LVCMOS or open-drain). Open-drain
requires an external pullup resistor.
- If the Interrupt is enabled and selected as a status
output, configure the flag polarity and the mask bits for any interrupt
source, and the combinational OR gate, as needed.
- Consider the following guidelines for designing the power supply:
- Outputs with identical frequency or integer-related (harmonic) frequencies can share a common filtered power supply.
- Example: 156.25-MHz and 312.5-MHz outputs on OUT[4:5] and OUT[6:7] can share a filtered VDDO supply, while 100-MHz, 50-MHz, and 25-MHz outputs on OUT[0:1] and OUT[2:3] can share a separate VDDO supply.
- See Section 9.1.6.