The XO input is the reference clock for the fractional-N APLLs when the APLLs are not used in cascade mode. The XO input determines the output frequency accuracy and stability in free-run or holdover modes.

For proper DPLL operation, the XO frequency must have a non-integer relationship with the VCO frequency so the respective APLL N divider has a fractional divider ratio. For APLL-only mode, the XO frequency can have an integer or fractional relationship with the VCOs frequencies.

For applications requiring DPLL functionality, such as SyncE and PTP/IEEE-1588 for eCPRI, the XO input can be driven by a TCXO, OCXO, or external traceable clock that conforms to the frequency accuracy and holdover stability required by the applicable synchronization standard. TCXO and OCXO frequencies of 13, 14.4, 19.2, 19.44, 24, 25, 27, 38.88, 48, 49.152 and 54 MHz are commonly available and cost-effective options that allow the APLL3 to operate in fractional mode for a VCBO frequency of 2500 MHz.

An XO/TCXO/OCXO source with low frequency or high phase jitter/noise floor will have no impact on the APLL3 output jitter performance because the VCBO determines the jitter and phase noise over the 12-kHz to 20-MHz integration bandwidth. An XO doubler increasing the PFD frequency can be enabled for each APLL to further optimize close in phase noise performance.

The XO input buffer has programmable input on-chip termination and AC-coupled input biasing configurations as shown in Figure 8-8. The buffered XO path also drives the input monitoring blocks.

Table 8-1 lists the typical XO input buffer configurations for common clock interface types.