Each APLL VCO post-divider supports an independently programmable divider.

APLL2 has one VCO post-divider clock (P1: ÷2 to ÷13) available for distribution to all outputs.

APLL1 has two VCO post-dividers. The primary VCO post-divider clock (P1: ÷2 to ÷7) is distributed for OUT0, OUT1, OUT2 and OUT3 in LMK5B33414. The secondary APLL1 VCO post-divider clock (P2: ÷2 to ÷7) is distributed for OUT0 and OUT1 in the LMK5B33414.

APLL3 has one VCO post-divider paired with an optional divide by 2. The VCO3 post-divider is comprised of a programmable divide by 8 followed by an optional divide by 2. The APLL3 post-divider clock div8 (÷2 to ÷8) or div8 & div2 (÷10, ÷12,÷14, ÷16) can be distributed to all 4 output banks in LMK5B33414. If the system use case requires sourcing multiple frequencies from APLL3 that cannot be supported from a single post-divider value, then bypass the VCO3 post-divider by setting VCO3 post-divider = 1 and program the individual channel dividers to obtain the desired output frequencies.