Each output driver can automatically mute its clock when the selected output mux clock source is invalid, as configured by its MUTE enable field. The source can be invalid based on the LOL status of each PLL by configuring the APLL and DPLL mute control bits (MUTE_APLLx_LOCK, MUTE_DPLLx_LOCK, MUTE_DPLLx_PHLOCK). When auto-mute is disabled or bypassed (OUT_x_y_MUTE_EN = 0), the output clock can have incorrect frequency or be unstable before and during the VCO calibration.