When DPLL operation is enabled, the clock source on the XO pin determines the free-run and holdover frequency stability and accuracy of the output clocks. The VCBO determines the APLL3 output clock phase noise and jitter performance over the 12-kHz to 20-MHz integration band, regardless of the frequency and jitter of the XO pin input. This increased immunity from reference noise degradation allows the APLL3 to use a cost-effective, low-frequency TCXO or OCXO as the external XO input while still maintaining standards-compliant frequency stability and low loop bandwidth (≤10 Hz) required for SyncE and PTP synchronization applications. APLL1 and APLL2 with standard LC type VCOs can be optimized for best jitter performance over the DC to 100-kHz integration band by using a wide loop bandwidth with a clean reference and a high phase detector frequency. When encountering system performance limitations arising from XO frequency or phase noise, there are unique cascading options to provide a clean high frequency reference for APLL1 and APLL2. The LMK5B33414 allows selecting the divided output from the VCBO (APLL3 Cascaded) which can significantly reduce APLL1 and APLL2 output RMS jitter.

If DCO mode is enabled on a DPLL, a frequency deviation step value (FDEV) can be programmed and used to adjust (increment or decrement) the DPLL's FB divider numerator. The DCO frequency adjustment effectively propagates through the APLL domain to the output clocks and any cascaded DPLL/APLL domains.

The programmed DPLL loop bandwidth (BW_DPLL) should be lower than all of the following:

1. 1/100th of the DPLL TDC rate.
2. 1/10th the APLL loop bandwidth.
3. The maximum DPLL bandwidth setting of 4 kHz.