In case the VDD core supplies ramp with a non-monotonic manner or with a slow ramp time from 0 V to 3.135 V of over 100 ms, TI recommends to delay the VCO calibration until after all of the core supplies have ramped above 3.135 V. This could be achieved by delaying the PD# low-to-high transition with one of the methods described in Section 9.1.6.3.

If any core supply cannot ramp above 3.135 V before the PD# low-to-high transition, it is acceptable to issue a device soft-reset after all core supplies have ramped to manually trigger the VCO calibration and PLL start-up sequence.