Zero-delay mode synchronization can be enabled to achieve zero phase delay between the selected DPLL reference input clock and the selected zero-delay feedback clock. Figure 8-30 shows how the OUT0 clock can internally feedback to any DPLL as the zero-delay output clock. Zero-delay mode is primarily implemented to achieve deterministic phase relationship between an input and selected outputs such as 1-PPS input to 1-PPS outputs or 156.25-MHz input to 156.25-MHz outputs.

There is no need to route external clock signals from output to input as the zero-delay feedback clock from OUT0 is routed internally to the device. Alternatively to OUT0, OUT4 may be used for DPLL2 internal ZDM feedback and OUT10 may be used for DPLL3 internal ZDM feedback.

1-PPS phase alignment is able to re-establish with the phase slew control and ZDM. For 1-PPS and ZDM, hitless switching must be enabled to prevent the DPLL from becoming unlocked. After performing hitless switching, the phase slew control can reduce the phase build-out back to 0 at a controlled rate. To lock to a 1-PPS signal using ZDM mode, the output static delay or DPLLx_PH_OFFSET must be programmed to zero out the phase error between the 1-PPS input and 1-PPS feedback clock. See Section 8.4.7 for an example of how input to output phase error in the DPLLx_PH_OFFSET field is calculated to apply fine adjustments less than 1-ps.