The DPLL supports a programmable loop bandwidth from 10 mHz to 4 kHz and can achieve jitter peaking below 0.1 dB (typical). The low-pass jitter transfer characteristic of the DPLL attenuates its reference input noise with up to 60-dB/decade roll-off above the loop bandwidth.

The DPLL loop filter output controls the fractional numerator of APLL to steer the VCO frequency into lock with the selected DPLL reference input.