All output channels share eight (LMK5C33216) output muxes. Each output mux for the OUT0 and OUT1 channels can individually select a source among XO, the PLL1 VCO clocks (P1 or P2), the PLL2 VCO clock (P1), the PLL3 VCO clock, and the references Mux clock. Either OUT2 or OUT3 has one output Mux respectively, which can source from PLL1 VCO clocks (P1 or P2), the PLL2 VCO clock (P1). Either OUT14 or OUT15 has one output Mux respectively, which can source from the PLL1 VCO clocks (P1), the PLL2 VCO clock (P1) and the PLl3 VCO clocks (P1). OUT4 to OUT7 share one Mux, OUT8 to OUT13 share one Mux. These two Muxes can source from the PLL2 VCO clock (P1) and the PLL3 VCO clock. OUT4 and OUT6 also can source from the PLL2 VCO clock (P2) directly.