The DPLL domain has a tuning word history monitor block that determines the initial output frequency accuracy upon entry into holdover. Once in holdover the stability of the reference clock (on XO input) determines the long-term stability and accuracy of the output frequency. The tuning word can be updated from one of three sources depending on the DPLL operating mode:

1. Locked Mode: from the output of the digital loop filter when locked
2. Holdover Mode: from the final output of the history monitor
3. Free Run Mode: from the free-run tuning word register (user defined)

When the history monitor is enabled and the DPLL is locked, the device averages the reference input frequency by accumulating history from the digital loop filter output during a programmable averaging time (T_AVG) set by DPLLx_HIST_TIMER. Once the input becomes invalid, the final tuning word value is stored to determine the initial holdover frequency accuracy. Generally, a longer T_AVG time will produce a more accurate initial holdover frequency.

Because history data could be corrupted if a tuning word update occurs while the input clock is failing and before it is detected by the input monitors the most recent collected average is ignored. So the actual history used will be between greater than T_AVG but less than 2 × T_AVG. Any in progress accumulation is ignored.

The tuning word history is initially cleared after a device hard reset or soft reset. After the DPLL locks to a new reference, the history monitor waits for the first T_AVG timer to expire before storing the first tuning word value and begins to accumulate history. The history monitor will not clear the previous history value during reference switchover or holdover exit. The history can be manually cleared or reset by toggling the history enable bit (DPLLx_HIST_EN = 1 → 0 → 1), if needed.

When no tuning word history exists, the free-run tuning word value (DPLLx_FREE_RUN) is used and determines the initial holdover output frequency accuracy.