Figure 9-4 shows an example where DPLL1 and DPLL2 is in cascaded mode from APLL3. APLL1, APLL2 and APLL3 lock their VCO frequency to the external XO input and operates in free-run mode without valid reference input. In this example, DPLL3 is the main DPLL, DPLL1 and DPLL2 are cascaded DPLLs.

Once a valid DPLL reference input is detected, the main DPLL begins lock acquisition. The DPLL3 TDC compares the phase of the selected reference input clock with the FB divider clock from the respective VCO and generates a digital correction word corresponding to the phase error. The correction word is filtered by the DLF, and the DLF output adjusts the APLL N divider SDM to pull the VCO frequency into lock with the reference input.

Cascading of DPLLs provides clean, low jitter output clocks synchronized with DPLL3. Note in cascaded DPLL mode, the best jitter performance and frequency stability will be achieved after DPLL3 locked.

DPLL3 lock status may not necessarily impact DPLL1 and DPLL2 lock status. If APLL3 is in free-run mode or holdover mode, and the VCBO frequency offset ppm value is still a valid reference for DPLL1 and DPLL2, then cascaded DPLL1, APLL1, DPLL2 and APLL2 are able to maintain lock status, while APLL1 and APLL2 outputs track the same frequency offset as APLL3. When all enabled DPLLs and APLLs are locked, all enabled outputs will be synchronized to the reference selected by the main DPLL.