Each DPLL reference clock input is independently monitored for input validation before it is qualified and available for selection by the DPLL. The reference monitoring blocks include frequency, missing pulse, and runt pulse monitors. For a 1-PPS input, the phase valid monitor is supported, while the frequency, missing pulse, and runt pulse monitors are not supported and must be disabled. A validation timer sets the minimum time for all enabled reference monitors to be clear of flags before an input is qualified.

The enablement and valid threshold for all reference monitors and validation timers are programmable per input. The reference monitors and validation timers are optional to enable, but are critical to achieve reliable DPLL lock and optimal transient performance during holdover or switchover events, and are also used to avoid selection of an unreliable or intermittent clock input. If a given detector is not enabled, it will not set a flag and will be ignored. The status flag of any enabled detector can be observed through the status pins for any reference input (selected or not selected). The status flags of the enabled detectors can also be read through the status bits for the selected input of the DPLL.