Once the DPLL locks, the APLL output clocks are frequency and phase locked to the selected DPLL reference input clock. While the DPLL is locked, the APLL output clocks will not be affected by frequency drift on the XO input. The DPLL has a programmable frequency lock detector and phase lock detectors to indicate loss-of-frequency lock (LOFL) and loss-of-phase lock (LOPL) status flags, which can be observed through the status pins or status bits. Once frequency lock is detected (LOFL → 0), the tuning word history monitor (if enabled) will begin to accumulate historical averaging data used to determine the initial output frequency accuracy upon entry into holdover mode.