Any GPIO pin can be configured as a device interrupt output pin. The interrupt logic configuration is set through registers. When the interrupt logic is enabled, the interrupt output can be triggered from any combination of interrupt status indicators, including LOS for the XO, LOR for the selected DPLL input, LOL for APLL1, APLL2, and the DPLL, and holdover and switchover events for the DPLL. When the interrupt polarity is set high, a rising edge on the live status bit will assert its interrupt flag (sticky bit). Otherwise, when the polarity is set low, a falling edge on the live status bit will assert its interrupt flag. Any individual interrupt flag can be masked so it does not trigger the interrupt output. The unmasked interrupt flags are combined by the AND/OR gate to generate the interrupt output, which can be selected on either status pin.

When a system host detects an interrupt from the device, the host can read the interrupt flag or sticky registers to identify which bits were asserted to resolve the fault conditions in the system. After the system faults have been resolved, the host can clear the interrupt output by writing 1 to the self clearing INT_CLR field.