If VDD or VDDO supplies are driven from different supply sources, TI recommends to start the PLL calibration after all of the supplies have ramped above 3.135 V. This can be realized by delaying the PD# low-to-high transition. The PD# input incorporates a 200-kΩ resistor to VDD_IN and as shown in Figure 10-2. A capacitor from the PD# pin to GND can be used to form an RC time constant with the internal pullup resistor. This RC time constant can be designed to delay the low-to-high transition of PD# until all the core supplies have ramped above 3.135 V. It is recommended for VDDO supply pins to ramp before VDD supply pins.

Alternatively, the PD# pin can be driven high by a system host or power management device to delay the device power-up sequence until all supplies have ramped.

As described in Section 10.1.6, it is necessary for the XO reference to be valid after PD# decision point 2 to ensure sucessful APLL1/VCO1 and APLL2/VCO2 calibration, or DPLL3 valid reference.