Output SYNC can be used to phase-align two or more output clocks with a common rising edge by allowing the output dividers to exit reset on the same PLL output clock cycle. Any output dividers selecting the same PLL output can be synchronized together as a SYNC group by triggering a SYNC event through the hardware pin or software bit.

The following requirements must be met to establish a SYNC group for two or more output channels:

• Output dividers have their respective sync enable bit set (OUT_x_y_DIV_SYNC_EN = 1).
• SYSREF dividers have their additional respective sync enable bit set (OUT_x_y_SR_DIV_SYNC_EN = 1), work with above set (OUT_x_y_DIV_SYNC_EN = 1)
• Output dividers have their output mux selecting the same PLL output.
• The PLL (post-divider) output has its sync enable bit set (for example, PLL1_PRI_DIV_SYNC_EN = 1).
• SYNC_EN = 1

A SYNC event can be asserted by either a GPIOx pin programmed for SYNC input with GPIOx_MODE = 31 or the SYNC_SW register bit (active high). When SYNC is asserted, the SYNC-enabled dividers are held in reset and clock outputs are low. When SYNC is deasserted, the outputs from a common PLL will start with their initial clock phases synchronized or aligned. SYNC can also be used to set a low state on any SYNC-enabled outputs to prevent output clocks from being distributed to downstream devices until they are configured and ready to accept the incoming clock.

Output channels with their sync disabled (OUT_x_y_DIV_SYNC_EN = 0) will not be affected by a SYNC event and will continue normal output operation as configured. VCO post-divider clocks must be enabled for synchronization to ensure the dividers they drive are synchronized accurately. However, any output deriving a clock from a reset VCO post-divider will not be valid during SYNC, even if the channel divider is not selected for SYNC. VCO post-dividers not selected for synchronization do not stop running during the SYNC so they can continue to source output channels that do not require synchronization. Output dividers with divide-by-1 (divider bypass mode) are not gated during the SYNC event.