米6体育平台手机版

ZHCSMJ6B November 2020 – March 2021 LMK5C33216

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

RGC|64
- MPQF125F

散热焊盘机械数据 (封装 | 引脚)

RGC|64
- QFND280F

订购信息

7.5 Electrical Characteristics

Over Recommended Operating Conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
IDD_PD#	Total Supply Current (all supply pins, 3.3 V)	Device powered-down (PD# pin held low)		132		mA
IDD_CFG1	Total Supply Current (all supply pins, 3.3 V)	DPLL3 with 10 MHz input. APLL2 = 5625 MHz, APLL3 = 2457.6 MHz. Outputs: 4x 491.52 MHz HSDS. 4x 7.68 MHz HSDS SYSREF. 2x 312.5 MHz LVDS.		875	1050	mA
Reference Input Characteristics (INx)
f_IN	Input frequency range	INx; Single Ended - LVCMOS input	1E-6		200	MHz
f_IN	Input frequency range	INx; Differential input	5		800	MHz
V_IH	LVCMOS Input high voltage	DC-coupled input mode	1.2		VDD + 0.3	V
V_IL	LVCMOS Input low voltage	DC-coupled input mode			0.5	V
V_IN-SE	Single-ended input voltage swing	AC-coupled input mode	0.4		2	V_pp
V_IN-DIFF	Differential input voltage swing, peak-peak (\|V_P– V_N\| x 2)	Differential input	0.4		2	V_pp
V_ICM	Input Common Mode	Differential input	0.1		2	V
dV/dt	Input slew rate	Single-ended input, non-driven input tied to GND	0.2	0.5		V/ns
dV/dt	Input slew rate	Differential input	0.2	0.5		V/ns
IDC	Input Clock Duty Cycle	Non 1 PPS signal	40		60	%
t_PULSE-1PPS	1PPS pulse width for input	1 PPS signal	100			ns
I_IN-DC	DC input leakage current	Single pin INx_P or INx_N, 50-Ω and 100-Ω internal terminations disabled, AC coupled mode enabled or disabled	-350		350	µA
XO/TCXO Input Characteristics (XO)
f_CLK	Input frequency range		10		100	MHz
V_IH	LVCMOS Input high voltage	DC-coupled input mode	1.4		VDD + 0.3	V
V_IL	LVCMOS Input low voltage	DC-coupled input mode			0.8	V
V_IN-SE	Single-ended input voltage swing	AC-coupled input mode	0.4		VDD + 0.3	V_pp
dV/dt	Input slew rate		0.2	0.5		V/ns
IDC	Input duty cycle		40		60	%
I_IN-DC	DC Input leakage current	Single pin XO_P, 50-Ω and 100-Ω internal terminations disabled	-350		350	µA
APLL/VCO Characteristics
f_VCO1	VCO1 Frequency range		4.8		5.35	GHz
f_VCO2	VCO2 Frequency range		5.6		5.95	GHz
f_VCO3	VCO3 Frequency range		2.457477120	2.4576	2.457722880	GHz
LVDS Output Characteristics (OUTx)
f_OUT	Maximum output frequency⁽²⁾		1000			MHz
V_OD	Output voltage swing (\|V_OH - V_OL\|)	OUT_x_AMP = 0, V_OS = 1.2 V		300		mV
		OUT_x_AMP = 1, V_OS = 1.2 V		400		mV
		OUT_x_AMP = 2, V_OS = 1.2 V		500		mV
		OUT_x_AMP = 3, V_OS 1.2 V		600		mV
V_OUT-DIFF	Differential output voltage swing, peak-to-peak			2×V_OD		V
V_OS	Output common mode	OUT_x_AMP = 1, DC shift setting 2		0.7		V
		OUT_x_AMP = 1, DC shift setting 4		0.8		V
		OUT_x_AMP = 1, DC shift setting 6		1.0		V
		OUT_x_AMP = 1, DC shift setting 8		1.2		V
		OUT_x_AMP = 1, DC shift setting 10		1.4		V
		OUT_x_AMP = 1, DC shift setting 12		1.6		V
t_SK	Output-to-output skew, same group⁽⁴⁾	Same post divider, output divide values, and output format			50	ps
t_{SK_GRP}	Output-to-output skew, between groups⁽⁴⁾	Same post divider, output divide values, and output format. Not including OUT14 and OUT15.			80	ps
t_{SK_GRP}	Output-to-output skew, between groups⁽⁴⁾	Same post divider, output divide values, and output format			150	ps
t_R/t_F	Output rise/fall time	20% to 80%, < 500 MHz		150	300	ps
t_R/t_F	Output rise/fall time	± 100 mV around center point		50	150	ps
PN_FLOOR	Output phase noise floor⁽³⁾ (f_OFFSET > 10 MHz)	122.88 MHz		-160		dBc/Hz
ODC	Output duty cycle⁽¹⁰⁾		45		55	%
HSDS Output Characteristics (OUTx)
f_OUT	Maximum output frequency⁽²⁾		1000			MHz
V_OD	Output voltage swing (\|V_OH - V_OL\|)	OUT_x_AMP = 1, boost off, V_OS = 1.2 V		400		mV
		OUT_x_AMP = 2, boost on, V_OS = 1.2 V		800		mV
		OUT_x_AMP = 3, boost off, V_OS = 1.2 V		600		mV
		OUT_x_AMP = 2, boost on, V_OS = 1.6 V		800		mV
		OUT_x_AMP = 3, boost on, V_OS = 1.2 V		850		mV
		OUT_x_AMP = 3, boost on, V_OS = 1.6 V		910		mV
V_OUT-DIFF	Differential output voltage swing, peak-to-peak			2×V_OD		V
V_OS	Output common mode	OUT_x_AMP = 1, boost on, DC shift setting 2		0.8		V
		OUT_x_AMP = 1, boost on, DC shift setting 4		1.0		V
		OUT_x_AMP = 1, boost on, DC shift setting 6		1.2		V
		OUT_x_AMP = 1, boost on, DC shift setting 8		1.4		V
		OUT_x_AMP = 1, boost on, DC shift setting 10		1.6		V
t_SK	Output-to-output skew, same group⁽⁴⁾	Same post divider, output divide values, and output format			50	ps
t_{SK_GRP}	Output-to-output skew, between groups⁽⁴⁾	Same post divider, output divide values, and output format. Not including OUT14 and OUT15.			80	ps
t_{SK_GRP}	Output-to-output skew, between groups⁽⁴⁾	Same post divider, output divide values, and output format.			150	ps
t_R/t_F	Output rise/fall time	20% to 80%, < 500 MHz		130	300	ps
t_R/t_F	Output rise/fall time	± 100 mV around center point		50	120	ps
PN_FLOOR	Output phase noise floor⁽³⁾ (f_OFFSET > 10 MHz)	122.88 MHz		-162		dBc/Hz
ODC	Output duty cycle⁽¹⁰⁾		45		55	%
LVPECL Output Characteristics (OUTx)
f_OUT	Maximum output frequency⁽²⁾		1000			MHz
V_OD	Output voltage swing (\|V_OH - V_OL\|)	OUT_x_AMP = 0, V_OS = 1.2 V		450		mV
		OUT_x_AMP = 1, V_OS = 1.2 V		600		mV
		OUT_x_AMP = 2, V_OS = 1.2 V		800		mV
		OUT_x_AMP = 2, V_OS = 1.6 V		700		mV
		OUT_x_AMP = 3, V_OS = 1.2 V		930		mV
		OUT_x_AMP = 3, V_OS = 1.6 V		840		mV
V_OUT-DIFF	Differential output voltage swing, peak-to-peak			2×V_OD		V
V_OS	Output common mode	OUT_x_AMP = 1, DC shift setting 2		0.7		V
		OUT_x_AMP = 1, DC shift setting 4		0.8		V
		OUT_x_AMP = 1, DC shift setting 6		1.0		V
		OUT_x_AMP = 1, DC shift setting 8		1.2		V
		OUT_x_AMP = 1, DC shift setting 10		1.4		V
		OUT_x_AMP = 1, DC shift setting 12		1.5		V
t_SK	Output-to-output skew, same group⁽⁴⁾	Same post divider, output divide values, and output format			50	ps
t_{SK_GRP}	Output-to-output skew, between groups⁽⁴⁾	Same post divider, output divide values, and output format			80	ps
t_{SK_GRP}	Output-to-output skew, between groups⁽⁴⁾	Same post divider, output divide values, and output format. Not including OUT14 and OUT15.			150	ps
t_R/t_F	Output rise/fall time	20% to 80%		150	300	ps
t_R/t_F	Output rise/fall time	± 100 mV around center point			200	ps
PN_FLOOR	Output phase noise floor⁽³⁾ (f_OFFSET > 10 MHz)	122.88 MHz		-162		dBc/Hz
ODC	Output duty cycle⁽¹⁰⁾		45		55	%
CML Open Collector Output Characteristics (OUTx)
f_OUT	Output frequency⁽²⁾	OUT4 or OUT6 CML open collector outputs			3000	MHz
V_OD	Output voltage swing (\|V_OH - V_OL\|)	Normal swing, OUT_x_AMP = 1, 2949.12 MHz	400	600		mV
V_OD	Output voltage swing (\|V_OH - V_OL\|)	High swing, OUT_x_AMP = 2, 2949.12 MHz	600	800		mV
V_OUT-DIFF	Differential output voltage swing, peak-to-peak			2×V_OD		V_pp
t_SK	Output-to-output skew	Same post divider, output divide values, and output type			50	ps
t_R/t_F	Output rise/fall time	20% to 80%, 2949.12 MHz		150	300	ps
t_R/t_F	Output rise/fall time	± 100 mV around center point, 2949.12 MHz		25	100	ps
PN_FLOOR	Output duty cycle⁽¹⁰⁾	2949.12 MHz		-156		dBc/Hz
ODC	Output duty cycle		45		55	%
1.8-V LVCMOS Output Characteristics (OUT0/1)
f_OUT	Maximum output frequency		200			MHz
V_OH	Output high voltage	I_OH = 1 mA	1.5			V
V_OL	Output low voltage	I_OL = 1 mA			0.2	V
I_OH	Output high current	V_O = 0.9 V		-18		mA
I_OL	Output low current	V_O = 0.9 V		18		mA
t_R/t_F	Output rise/fall time	20% to 80%		150		ps
t_SK	Output-to-output skew	Same post divider, output divide values, and output type			100	ps
t_SK	Output-to-output skew	Same post divider, output divide values, LVCMOS-to-DIFF			1.5	ns
PN_FLOOR	Output phase noise floor (f_OFFSET > 10 MHz)	66.66 MHz		-155		dBc/Hz
ODC	Output duty cycle⁽¹⁰⁾		45		55	%
R_OUT	Output impedance			50		Ω
2.65-V LVCMOS Output Characteristics (OUT0/1)
f_OUT	Maximum output frequency		200			MHz
V_OH	Output high voltage	I_OH = 1 mA	2.3			V
V_OL	Output low voltage	I_OL = 1 mA			0.2	V
I_OH	Output high current	V_O = 1.25 V		-25		mA
I_OL	Output low current	V_O = 1.25 V		25		mA
t_R/t_F	Output rise/fall time	20% to 80%		150		ps
t_SK	Output-to-output skew	Same post divider, output divide values, and output type			100	ps
t_SK	Output-to-output skew	Same post divider, output divide values, LVCMOS-to-DIFF			1.5	ns
PN_FLOOR	Output phase noise floor (f_OFFSET > 10 MHz)	66.66 MHz		-155		dBc/Hz
ODC	Output duty cycle⁽¹⁰⁾		45		55	%
R_OUT	Output impedance			50		Ω
3-Level Logic Input Characteristics (GPIO0, GPIO1, GPIO2, SCS_ADD)
V_IH	Input high voltage		1.4			V
V_IM	Input mid voltage		0.6		1	V
V_IM	Input mid voltage self-bias	Input floating with internal bias and PD# pulled low	0.7		0.9	V
V_IL	Input low voltage				0.4	V
I_IH	Input high current	V_IH = VDD	-40		40	µA
I_IL	Input low current	V_IL = GND	-40		40	µA
C_IN	Input capacitance			2		pF
2-Level Logic Input Characteristics (PD#, SCK, SDIO, SCS_ADD; GPIO0, GPIO1 and GPIO2 after power up)
V_IH	Input high voltage		1.2			V
V_IL	Input low voltage				0.4	V
I_IH	Input high current	V_IH = VDD, except PD#	-40		40	µA
I_IL	Input low current	V_IL = GND, except PD#	-40		40	µA
C_IN	Input capacitance			2		pF
Logic Output Characteristics (GPIO0, GPIO1, GPIO2, SDIO)
V_OH	Output high voltage	I_OH= 1 mA	2.4			V
V_OL	Output low voltage	I_OL= 1 mA			0.4	V
t_R/t_F	Output rise/fall time	20% to 80%, LVCMOS mode, 1 kΩ to GND		500		ps
SPI Timing Requirements (SDIO, SCK, SCS_ADD)
f_SCK	SPI clock rate				20	MHz
f_SCK	SPI clock rate; during SRAM read and write operations				5	MHz
t₁	SCS to SCK setup time (start communication cycle)		10			ns
t₂	SDI to SCK setup time		10			ns
t₃	SDI to SCK hold time		10			ns
t₄	SCK high time		25			ns
t₅	SCK low time		25			ns
t₆	SCK to SDO valid read-back data				20	ns
t₇	SCS pulse width		20			ns
t₈	SCK to SCS setup time (end communication cycle)		10			ns
I²C Timing Requirements (SDIO, SCK)
V_IH	Input high voltage		1.2			V
V_IL	Input low voltage				0.5	V
I_IH	Input leakage		-15		15	µA
V_OL	Output low voltage	I_OL = 3 mA			0.3	V
f_SCL	I²C clock rate	Standard			100	kHz
f_SCL	I²C clock rate	Fast mode			400	kHz
t_SU(START)	START condition setup time	SCL high before SDA low	0.6			µs
t_H(START)	START condition hold time	SCL low after SDA low	0.6			µs
t_W(SCLH)	SCL pulse width high		0.6			µs
t_W(SCLL)	SCL pulse width low		1.3			µs
t_SU(SDA)	SDA setup time		100			ns
t_H(SDA)	SDA hold time	SDA valid after SCL low	0		0.9	µs
t_R(IN)	SDA/SCL input rise time				300	ns
t_F(IN)	SDA/SCL input fall time				300	ns
t_F(OUT)	SDA output fall time	C_BUS ≤ 400 pF			300	ns
t_SU(STOP)	STOP condition setup time		0.6			µs
t_BUS	Bus free time between STOP and START		1.3			µs
Other Characteristics
t_PHO-VAR	Input-to-output phase offset variation over PVT	Zero delay mode, RF clocks only, INx = 122.88 MHz, OUTx = 2949.12 MHz or 2457.6 MHz or 1474.56 MHz or 1228.8 MHz or 737.28 MHz or 614.4 MHz or 153.6 MHz or 122.88 MHz	-200		200	ps
t_ANA-DEL-ERR	Analog delay error for any step setting⁽⁹⁾	VCBO = 2457.6 MHz, PLL3_PRI_DIV = ÷5, OUTx = 491.52 MHz, Analog Delay step = 32.8 ps	-16		16	ps
t_DIG-DEL	Digital delay step size on device clock and SYSREF outputs	SYSREF analog delay off for half cycle steps and OUT_x_y_SR_CH_DIV_BYPASS = 1		½ VCO post divider cycle
PSNR	Spur induced by power supply noise (V_N = 50 mVpp)⁽⁵⁾ ⁽⁶⁾	Vcc = 3.3V, HSDS, LVDS, and LVPECL output		-75		dBc
SPUR	Highest Spur level at 100 Hz to 40 MHz offset⁽⁶⁾ ⁽⁷⁾	f_OUTx = 122.88 MHz from VCO3, VCO2 = 5625 MHz, and VCO1 = 5000 MHz		-90		dBc
SPUR	Highest spur level within12 kHz to 40 MHz band⁽⁶⁾ ⁽⁷⁾	f_OUTx = 122.88 MHz, AC-DIFF or LVDS (all outputs operating with differential level and no SYSREF)		-75		dBc
PLL Clock Output Performance Characteristics
RJ1	RMS phase jitter of DPLL1/APLL1 (12 kHz to 20 MHz)⁽³⁾ ⁽⁷⁾	XO = 38.88 MHz, APLL1 = 5000 MHz or 5156.25 MHz, OUTx = 312.5 or 322.265625 MHz, all differential output types		200	250	fs RMS
RJ2	RMS phase jitter of DPLL2/APLL2 (12 kHz to 20 MHz)⁽³⁾ ⁽⁷⁾	XO = 38.88 MHz, APLL2 = 5898.24 MHz or 5650 MHz, OUTx = 245.76 MHz or 312.5 MHz, all differential output types		120	180	fs RMS
RJ3	RMS phase jitter of DPLL3/APLL3 (12 kHz to 20 MHz)⁽³⁾ ⁽⁷⁾	XO = 38.88 MHz, APLL3 = 2457.6 MHz, OUTx = 245.76 MHz, all differential output types		50	80	fs RMS
RJ4	RMS phase jitter of DPLL3/APLL3 (12 kHz to 20 MHz)⁽³⁾ ⁽⁷⁾	XO = 38.88 MHz, APLL3 = 2457.6 MHz, OUTx = 491.52 MHz, all differential output types		40	70	fs RMS
PN-APLL3	Phase Noise of DPLL3/APLL3 at 800 kHz offset	38.88 MHz XO, VCO3 = 2457.6 MHz, 2457.6 MHz CML output		-147		dBc/Hz
PN_TDC	Output close-in phase noise for DPLL1 and DPLL2 (f_OFFSET = 100 Hz)	122.88 MHz AC-DIFF or LVDS, TCXO = 38.88 MHz, f_TDC > 20 MHz, DPLL-BW = 1 kHz		-116		dBc/Hz
PN_TDC	Output close-in phase noise for DPLL3 (f_OFFSET = 100 Hz)	122.88 MHz AC-DIFF or LVDS, TCXO = 38.88 MHz, f_TDC > 20 MHz, DPLL-BW = 1 kHz		-110		dBc/Hz
BW	DPLL bandwidth range⁽⁸⁾	Programmed bandwidth setting	0.01		4000	Hz
J_PK	DPLL closed-loop jitter peaking⁽¹¹⁾	f_IN = 25 MHz, f_OUT = 10 MHz, DPLL BW = 0.1 Hz or 10 Hz		0.1		dB
J_TOL	Jitter tolerance	Compliant with G.8262 Options 1 and 2, Jitter modulation = 10 Hz, 25.78125 Gbps		6455		UI p-p
t_HITLESS	Phase transient during hitless switch	Valid for a single switchover event between two clock inputs at the same frequency 122.88 MHz	-100		100	ps
f_HITLESS	Frequency transient during hitless switch	Valid for a single switchover event between two clock inputs at the same frequency 122.88 MHz	-10		10	ppb

(2) Total device current can be estimated by summing the individual IDD_x and IDDO_x per pin for all blocks enabled in a given configuration.

(5) Configuration A (All blocks on): f_REF[0:1] = 156.25 MHz, 10 MHz, f_XO = 38.88 MHz. All DPLLs and APLLs enabled, f_VCO1 = 5 GHz, f_VCO2 = 5.625 GHz, f_VCO3 = 2.4576 GHz, PLL1_P1 = 5, PLL2_P1 = 9, PLL3_P1 = 5. All outputs on.

(6) Configuration B (All blocks on): f_REF[0:1] = 25 MHz, f_XO = 38.88 MHz. DPLL[3:1]/APLL[3:1] enabled, f_VCO1 = 5.15625 GHz, f_VCO2 = 6.25 GHz, f_VCO3 = 2.4576 GHz, PLL1_P1 = 8, PLL2_P1 = 5

(1) In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all
input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input
slew rate is reduced.

(2) An output frequency over the f_OUT max spec is possible, but the output swing may be less than the V_OD min spec.

(3) Any output clock except OUT2, OUT3, OUT14, or OUT15.

(4) Output groups are (OUT0 and 1), (OUT2 and 3), (OUT4 to 7), (OUT8 to 13) and (OUT14 and 15).

(5) PSNR is the single-sideband spur level (in dBc) measured when sinusoidal noise with amplitude V_N and frequency between 100 kHz and 1 MHz is injected onto VDD and VDDO_x pins.

(6) DJ_SPUR (ps pk-pk) = [2 × 10^(dBc/20) / (π × f_OUT) × 1E6], where dBc is the PSNR or SPUR level (in dBc) and f_OUT is the output frequency (in MHz).

(7) Excludes output crosstalk and integer-boundary spurs.

(8) DPLL loop bandwidth must be less than 1/100 of TDC frequency and less than 1/10 of APLL loop bandwidth.

(9) Analog delay step size and worst case time error is a function of the input frequency to the SYSREF block and analog delay block configuration. Maximum analog delay error is half the analog delay step size.

(10) Parameter is specified for PLL outputs divided from either VCO domain.

(11) The TICS Pro software configures the closed-loop jitter peaking for 0.1 dB or less based on the programmed DPLL bandwidth setting.