ZHCSFA1C June   2016  – November 2017 LMK60A0-148351 , LMK60A0-148M , LMK60E0-156257 , LMK60E2-150M

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      引脚分配
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Supply
    6. 6.6  LVPECL Output Characteristics
    7. 6.7  LVDS Output Characteristics
    8. 6.8  HCSL Output Characteristics
    9. 6.9  OE Input Characteristics
    10. 6.10 Frequency Tolerance Characteristics
    11. 6.11 Power-On/Reset Characteristics (VDD)
    12. 6.12 PSRR Characteristics
    13. 6.13 PLL Clock Output Jitter Characteristics
    14. 6.14 Additional Reliability and Qualification
    15. 6.15 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Device Output Configurations
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Ensuring Thermal Reliability
      2. 9.1.2 Best Practices for Signal Integrity
      3. 9.1.3 Recommended Solder Reflow Profile
  10. 10器件和文档支持
    1. 10.1 相关链接
    2. 10.2 接收文档更新通知
    3. 10.3 社区资源
    4. 10.4 商标
    5. 10.5 静电放电警告
    6. 10.6 Glossary
  11. 11机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • SIA|6
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.11 Power-On/Reset Characteristics (VDD)

VDD = 3.3 V ± 5%, TA = -40°C to 85°C
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VTHRESH Threshold voltage(1) 2.72 2.95 V
VDROOP Allowable voltage droop(2) 0.1 V
tSTARTUP Start-up time (1) Time elapsed from VDD at 3.135 V to output enabled 10 ms
tOE-EN Output enable time(2) Time elapsed from OE at VIH to output enabled 50 µs
tOE-DIS Output disable time(2) Time elapsed from OE at VIL to output disabled 50 µs
(1) Ensured by characterization.
(2) Ensured by design.
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