The PLL in LMK61E07 can be configured to accommodate various output frequencies either through I²C programming interface or, in the absence of programming the PLL defaults stored in EEPROM are loaded on power up. The PLL can be configured by setting the Reference Doubler, Integrated PLL Loop Filter, Feedback Divider, and Output Divider. The corresponding register addresses and configurations are detailed in the description section of each block below.

For the PLL to operate in closed-loop mode, the following condition in Equation 1 has to be met.

where

• F_VCO: PLL/VCO Frequency (4.6 GHz to 5.6 GHz)
• F_REF: 50-MHz reference input
• D: Reference input doubler, 1=Disabled, 2=Enabled
• R: Reference input divider, 1=Divider bypass, 4=Divide-by-4
• INT: PLL feedback divider integer value (12 bits, 1 to 4095)
• NUM: PLL feedback divider fractional numerator value (22 bits, 0 to 4194303)
• DEN: PLL feedback divider fractional denominator value (22 bits, 1 to 4194303)

On LMK61E07, the output frequency is related to the VCO frequency as given in Equation 2.

where

• OUTDIV: Output divider value (9 bits, 5 to 511)

The output frequency step size for every bit change in the numerator of the PLL fractional feedback divider is given in Equation 3.