ZHCSH74B december 2017 – august 2023 LMK61E07
PRODUCTION DATA
The DEV_CTL register holds the control functions described in the following table.
| BIT NO. | FIELD | TYPE | DEFAULT | EEPROM | DESCRIPTION | |
|---|---|---|---|---|---|---|
| [7] | RESERVED | - | 0 | Y | Reserved. | |
| [6] | PLL_PDN | RW | 0 | Y | PLL Powerdown. The PLL_PDN bit determines whether PLL is automatically enabled and calibrated after a hardware reset. If the PLL_PDN bit is set to 1 during normal operation then PLL is disabled and the calibration circuit is reset. When PLL_PDN is then cleared to 0 PLL is re-enabled and the calibration sequence is automatically restarted. | |
| PLL_PDN | Value | |||||
| 0 | PLL Enabled | |||||
| 1 | PLL Disabled | |||||
| [5] | CMOS_SEL | RW | 0 | Y | Set to 0 for LMK61E07 . | |
| [4:2] | RESERVED[5:2] | RW | 0 | Y | Reserved. | |
| [1] | ENCAL | RWSC | 0 | N | Enable Frequency Calibration. Triggers PLL/VCO calibration on the PLL on 0 –> 1 transition of ENCAL. This bit is self-clearing and set to a 0 after PLL/VCO calibration is complete. In powerup or software rest mode, AUTOSTRT takes precedence. | |
| [0] | AUTOSTRT | RW | 1 | Y | Autostart. If AUTOSTRT is set to 1 the device will automatically attempt to achieve lock and enable outputs after a device reset. A device reset can be triggered by the power-on-reset or by writing to the SWR2PLL bit. If AUTOSTRT is 0 then the device will halt after the configuration phase, a subsequent write to set the AUTOSTRT bit to 1 will trigger the PLL Lock sequence. | |