The reference path has a divider and frequency doubler. The reference divider can be bypassed by programming R24[0] = 0 or can be set to divide-by-4 by programming R24[0] = 1. Enabling the divider results in a lower comparison frequency for the PLL and would result in a 6-dB increase in the in-band phase noise at the output of the LMK61E07 but would result in a finer frequency resolution at the output for every bit change in the numerator of fractional feedback divider. The reference doubler can be enabled by programming R34[5] = 1. Bypassing the divider allows for a higher comparison rate and improved in-band phase noise at the output of the LMK61E07. Enabling the doubler allows a higher comparison frequency for the PLL and would result in a 3-dB reduction in the in-band phase noise at the output of the LMK61E07. Enabling the doubler also results in higher reference and phase detector spurs which will be minimized by enabling the higher order components (R3, C3) of the loop filter and programming them to appropriate values. Disabling the doubler would result in a finer frequency resolution at the output for every bit change in the numerator of the fractional feedback divider and higher in-band phase noise on the device output than when the doubler is enabled. However, the reference and phase detector spurs would be lower on the device output than when the doubler is enabled.