The LMK61E07 features a fully integrated loop filter for the PLL that supports programmable loop bandwidth from 100 kHz to 1 MHz. The loop filter components, R2, C1, R3, and C3, can be configured by programming R36, R37, R38, and R39, respectively. The LMK61E07 features a fixed value of C2 of 10 nF. When the PLL is configured in fractional mode, R35[2] should be set to 1. When the reference doubler is disabled for integer mode PLL, R35[2] should be set to 0 and R38[6:0] should be set to 0x00. When the reference doubler is enabled for integer mode PLL, R35[2] should be set to 1 and R38 and R39 are written with the appropriate values. Figure 8-2 shows the loop filter structure of the PLL. It is important to set the PLL to the best possible bandwidth to minimize output jitter.

Figure 8-2 Loop Filter Structure of PLL